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GDB (API)
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GDB (API)
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#include "defs.h"#include "gdbcmd.h"#include "serial.h"#include "gdb_string.h"#include <time.h>#include <dos.h>#include <go32.h>#include <dpmi.h>Go to the source code of this file.
Defines | |
| #define | COM1ADDR 0x3f8 |
| #define | COM2ADDR 0x2f8 |
| #define | COM3ADDR 0x3e8 |
| #define | COM4ADDR 0x3e0 |
| #define | com_data 0 /* data register (R/W) */ |
| #define | com_dlbl 0 /* divisor latch low (W) */ |
| #define | com_ier 1 /* interrupt enable (W) */ |
| #define | com_dlbh 1 /* divisor latch high (W) */ |
| #define | com_iir 2 /* interrupt identification (R) */ |
| #define | com_fifo 2 /* FIFO control (W) */ |
| #define | com_lctl 3 /* line control register (R/W) */ |
| #define | com_cfcr 3 /* line control register (R/W) */ |
| #define | com_mcr 4 /* modem control register (R/W) */ |
| #define | com_lsr 5 /* line status register (R/W) */ |
| #define | com_msr 6 /* modem status register (R/W) */ |
| #define | COMTICK (1843200/16) |
| #define | SPEED_TOLERANCE 30 /* thousandths; real == desired +- 3.0% */ |
| #define | IER_ERXRDY 0x1 /* int on rx ready */ |
| #define | IER_ETXRDY 0x2 /* int on tx ready */ |
| #define | IER_ERLS 0x4 /* int on line status change */ |
| #define | IER_EMSC 0x8 /* int on modem status change */ |
| #define | IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ |
| #define | IIR_IMASK 0xf /* interrupt cause mask */ |
| #define | IIR_NOPEND 0x1 /* nothing pending */ |
| #define | IIR_RLS 0x6 /* receive line status */ |
| #define | IIR_RXRDY 0x4 /* receive ready */ |
| #define | IIR_RXTOUT 0xc /* receive timeout */ |
| #define | IIR_TXRDY 0x2 /* transmit ready */ |
| #define | IIR_MLSC 0x0 /* modem status */ |
| #define | FIFO_ENABLE 0x01 /* enable fifo */ |
| #define | FIFO_RCV_RST 0x02 /* reset receive fifo */ |
| #define | FIFO_XMT_RST 0x04 /* reset transmit fifo */ |
| #define | FIFO_DMA_MODE 0x08 /* enable dma mode */ |
| #define | FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ |
| #define | FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ |
| #define | FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ |
| #define | FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ |
| #define | CFCR_DLAB 0x80 /* divisor latch */ |
| #define | CFCR_SBREAK 0x40 /* send break */ |
| #define | CFCR_PZERO 0x30 /* zero parity */ |
| #define | CFCR_PONE 0x20 /* one parity */ |
| #define | CFCR_PEVEN 0x10 /* even parity */ |
| #define | CFCR_PODD 0x00 /* odd parity */ |
| #define | CFCR_PENAB 0x08 /* parity enable */ |
| #define | CFCR_STOPB 0x04 /* 2 stop bits */ |
| #define | CFCR_8BITS 0x03 /* 8 data bits */ |
| #define | CFCR_7BITS 0x02 /* 7 data bits */ |
| #define | CFCR_6BITS 0x01 /* 6 data bits */ |
| #define | CFCR_5BITS 0x00 /* 5 data bits */ |
| #define | MCR_LOOPBACK 0x10 /* loopback */ |
| #define | MCR_IENABLE 0x08 /* output 2 = int enable */ |
| #define | MCR_DRS 0x04 /* output 1 = xxx */ |
| #define | MCR_RTS 0x02 /* enable RTS */ |
| #define | MCR_DTR 0x01 /* enable DTR */ |
| #define | LSR_RCV_FIFO 0x80 /* error in receive fifo */ |
| #define | LSR_TSRE 0x40 /* transmitter empty */ |
| #define | LSR_TXRDY 0x20 /* transmitter ready */ |
| #define | LSR_BI 0x10 /* break detected */ |
| #define | LSR_FE 0x08 /* framing error */ |
| #define | LSR_PE 0x04 /* parity error */ |
| #define | LSR_OE 0x02 /* overrun error */ |
| #define | LSR_RXRDY 0x01 /* receiver ready */ |
| #define | LSR_RCV_MASK 0x1f |
| #define | MSR_DCD 0x80 |
| #define | MSR_RI 0x40 |
| #define | MSR_DSR 0x20 |
| #define | MSR_CTS 0x10 |
| #define | MSR_DDCD 0x08 |
| #define | MSR_TERI 0x04 |
| #define | MSR_DDSR 0x02 |
| #define | MSR_DCTS 0x01 |
| #define | FIFO_TRIGGER FIFO_TRIGGER_4 |
| #define | CBSIZE 4096 |
| #define | RAWHZ 18 |
| #define | COUNT(x) |
| #define | ICU_BASE 0x20 |
| #define | ICU_OCW2 (ICU_BASE + 0) |
| #define | ICU_MASK (ICU_BASE + 1) |
| #define | NINTR 8 |
| #define | inb(p, a) inportb((p)->base + (a)) |
| #define | outb(p, a, v) outportb((p)->base + (a), (v)) |
| #define | disable() asm volatile ("cli"); |
| #define | enable() asm volatile ("sti"); |
| #define | ISRNAME(x) dos_comisr##x |
| #define | ISR(x) static void ISRNAME(x)(void) {dos_comisr(x);} |
| #define | divrnd(n, q) (((n) * 2 / (q) + 1) / 2) /* Divide and round off. */ |
Typedefs | |
| typedef unsigned long | u_long |
Functions | |
| ISR (0) | |
| int | gdb_pipe (int pdes[2]) |
| void | _initialize_ser_dos (void) |
Variables | |
| unsigned char | icu_oldmask |
| initialize_file_ftype | _initialize_ser_dos |
| #define CBSIZE 4096 |
Definition at line 139 of file ser-go32.c.
| #define CFCR_5BITS 0x00 /* 5 data bits */ |
Definition at line 99 of file ser-go32.c.
| #define CFCR_6BITS 0x01 /* 6 data bits */ |
Definition at line 98 of file ser-go32.c.
| #define CFCR_7BITS 0x02 /* 7 data bits */ |
Definition at line 97 of file ser-go32.c.
| #define CFCR_8BITS 0x03 /* 8 data bits */ |
Definition at line 96 of file ser-go32.c.
| #define CFCR_DLAB 0x80 /* divisor latch */ |
Definition at line 88 of file ser-go32.c.
| #define CFCR_PENAB 0x08 /* parity enable */ |
Definition at line 94 of file ser-go32.c.
| #define CFCR_PEVEN 0x10 /* even parity */ |
Definition at line 92 of file ser-go32.c.
| #define CFCR_PODD 0x00 /* odd parity */ |
Definition at line 93 of file ser-go32.c.
| #define CFCR_PONE 0x20 /* one parity */ |
Definition at line 91 of file ser-go32.c.
| #define CFCR_PZERO 0x30 /* zero parity */ |
Definition at line 90 of file ser-go32.c.
| #define CFCR_SBREAK 0x40 /* send break */ |
Definition at line 89 of file ser-go32.c.
| #define CFCR_STOPB 0x04 /* 2 stop bits */ |
Definition at line 95 of file ser-go32.c.
| #define COM1ADDR 0x3f8 |
Definition at line 34 of file ser-go32.c.
| #define COM2ADDR 0x2f8 |
Definition at line 35 of file ser-go32.c.
| #define COM3ADDR 0x3e8 |
Definition at line 36 of file ser-go32.c.
| #define COM4ADDR 0x3e0 |
Definition at line 37 of file ser-go32.c.
Definition at line 46 of file ser-go32.c.
Definition at line 39 of file ser-go32.c.
| #define com_dlbh 1 /* divisor latch high (W) */ |
Definition at line 42 of file ser-go32.c.
| #define com_dlbl 0 /* divisor latch low (W) */ |
Definition at line 40 of file ser-go32.c.
| #define com_fifo 2 /* FIFO control (W) */ |
Definition at line 44 of file ser-go32.c.
Definition at line 41 of file ser-go32.c.
Definition at line 43 of file ser-go32.c.
Definition at line 45 of file ser-go32.c.
Definition at line 48 of file ser-go32.c.
Definition at line 47 of file ser-go32.c.
Definition at line 49 of file ser-go32.c.
| #define COMTICK (1843200/16) |
Definition at line 57 of file ser-go32.c.
| #define COUNT | ( | x | ) |
Definition at line 165 of file ser-go32.c.
| #define disable | ( | ) | asm volatile ("cli"); |
Definition at line 241 of file ser-go32.c.
| #define divrnd | ( | n, | |
| q | |||
| ) | (((n) * 2 / (q) + 1) / 2) /* Divide and round off. */ |
| #define enable | ( | ) | asm volatile ("sti"); |
Definition at line 242 of file ser-go32.c.
| #define FIFO_DMA_MODE 0x08 /* enable dma mode */ |
Definition at line 81 of file ser-go32.c.
| #define FIFO_ENABLE 0x01 /* enable fifo */ |
Definition at line 78 of file ser-go32.c.
| #define FIFO_RCV_RST 0x02 /* reset receive fifo */ |
Definition at line 79 of file ser-go32.c.
| #define FIFO_TRIGGER FIFO_TRIGGER_4 |
Definition at line 136 of file ser-go32.c.
| #define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ |
Definition at line 82 of file ser-go32.c.
| #define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ |
Definition at line 85 of file ser-go32.c.
| #define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ |
Definition at line 83 of file ser-go32.c.
| #define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ |
Definition at line 84 of file ser-go32.c.
| #define FIFO_XMT_RST 0x04 /* reset transmit fifo */ |
Definition at line 80 of file ser-go32.c.
| #define ICU_BASE 0x20 |
Definition at line 169 of file ser-go32.c.
Definition at line 171 of file ser-go32.c.
Definition at line 170 of file ser-go32.c.
| #define IER_EMSC 0x8 /* int on modem status change */ |
Definition at line 64 of file ser-go32.c.
| #define IER_ERLS 0x4 /* int on line status change */ |
Definition at line 63 of file ser-go32.c.
| #define IER_ERXRDY 0x1 /* int on rx ready */ |
Definition at line 61 of file ser-go32.c.
| #define IER_ETXRDY 0x2 /* int on tx ready */ |
Definition at line 62 of file ser-go32.c.
| #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ |
Definition at line 67 of file ser-go32.c.
| #define IIR_IMASK 0xf /* interrupt cause mask */ |
Definition at line 68 of file ser-go32.c.
| #define IIR_MLSC 0x0 /* modem status */ |
Definition at line 74 of file ser-go32.c.
| #define IIR_NOPEND 0x1 /* nothing pending */ |
Definition at line 69 of file ser-go32.c.
| #define IIR_RLS 0x6 /* receive line status */ |
Definition at line 70 of file ser-go32.c.
| #define IIR_RXRDY 0x4 /* receive ready */ |
Definition at line 71 of file ser-go32.c.
| #define IIR_RXTOUT 0xc /* receive timeout */ |
Definition at line 72 of file ser-go32.c.
| #define IIR_TXRDY 0x2 /* transmit ready */ |
Definition at line 73 of file ser-go32.c.
Definition at line 239 of file ser-go32.c.
Definition at line 355 of file ser-go32.c.
| #define ISRNAME | ( | x | ) | dos_comisr##x |
Definition at line 354 of file ser-go32.c.
| #define LSR_BI 0x10 /* break detected */ |
Definition at line 112 of file ser-go32.c.
| #define LSR_FE 0x08 /* framing error */ |
Definition at line 113 of file ser-go32.c.
| #define LSR_OE 0x02 /* overrun error */ |
Definition at line 115 of file ser-go32.c.
| #define LSR_PE 0x04 /* parity error */ |
Definition at line 114 of file ser-go32.c.
| #define LSR_RCV_FIFO 0x80 /* error in receive fifo */ |
Definition at line 109 of file ser-go32.c.
| #define LSR_RCV_MASK 0x1f |
Definition at line 117 of file ser-go32.c.
| #define LSR_RXRDY 0x01 /* receiver ready */ |
Definition at line 116 of file ser-go32.c.
| #define LSR_TSRE 0x40 /* transmitter empty */ |
Definition at line 110 of file ser-go32.c.
| #define LSR_TXRDY 0x20 /* transmitter ready */ |
Definition at line 111 of file ser-go32.c.
| #define MCR_DRS 0x04 /* output 1 = xxx */ |
Definition at line 104 of file ser-go32.c.
| #define MCR_DTR 0x01 /* enable DTR */ |
Definition at line 106 of file ser-go32.c.
| #define MCR_IENABLE 0x08 /* output 2 = int enable */ |
Definition at line 103 of file ser-go32.c.
| #define MCR_LOOPBACK 0x10 /* loopback */ |
Definition at line 102 of file ser-go32.c.
| #define MCR_RTS 0x02 /* enable RTS */ |
Definition at line 105 of file ser-go32.c.
| #define MSR_CTS 0x10 |
Definition at line 123 of file ser-go32.c.
| #define MSR_DCD 0x80 |
Definition at line 120 of file ser-go32.c.
| #define MSR_DCTS 0x01 |
Definition at line 127 of file ser-go32.c.
| #define MSR_DDCD 0x08 |
Definition at line 124 of file ser-go32.c.
| #define MSR_DDSR 0x02 |
Definition at line 126 of file ser-go32.c.
| #define MSR_DSR 0x20 |
Definition at line 122 of file ser-go32.c.
| #define MSR_RI 0x40 |
Definition at line 121 of file ser-go32.c.
| #define MSR_TERI 0x04 |
Definition at line 125 of file ser-go32.c.
| #define NINTR 8 |
Definition at line 177 of file ser-go32.c.
Definition at line 240 of file ser-go32.c.
| #define RAWHZ 18 |
Definition at line 141 of file ser-go32.c.
| #define SPEED_TOLERANCE 30 /* thousandths; real == desired +- 3.0% */ |
Definition at line 58 of file ser-go32.c.
| typedef unsigned long u_long |
Definition at line 133 of file ser-go32.c.
| void _initialize_ser_dos | ( | void | ) |
Definition at line 916 of file ser-go32.c.
Definition at line 876 of file ser-go32.c.
| ISR | ( | 0 | ) |
Definition at line 357 of file ser-go32.c.
| unsigned char icu_oldmask |
Definition at line 174 of file ser-go32.c.
1.7.6.1