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GDB (API)
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GDB (API)
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00001 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 00002 00003 Copyright (C) 2003-2013 Free Software Foundation, Inc. 00004 00005 This file is part of GDB. 00006 00007 This program is free software; you can redistribute it and/or modify 00008 it under the terms of the GNU General Public License as published by 00009 the Free Software Foundation; either version 3 of the License, or 00010 (at your option) any later version. 00011 00012 This program is distributed in the hope that it will be useful, 00013 but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 GNU General Public License for more details. 00016 00017 You should have received a copy of the GNU General Public License 00018 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 00019 00020 00021 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 00022 whenever the "tdep" structure changes in an incompatible way. */ 00023 00024 #define XTENSA_TDEP_VERSION 0x60 00025 00026 /* Xtensa register type. */ 00027 00028 typedef enum 00029 { 00030 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 00031 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 00032 xtRegisterTypeUserReg, /* User defined registers (rur). */ 00033 xtRegisterTypeTieRegfile, /* User define register files. */ 00034 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 00035 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 00036 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 00037 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 00038 xtRegisterTypeVirtual, /* PC, FP. */ 00039 xtRegisterTypeUnknown 00040 } xtensa_register_type_t; 00041 00042 00043 /* Xtensa register group. */ 00044 00045 #define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ 00046 00047 typedef enum 00048 { 00049 xtRegisterGroupUnknown = 0, 00050 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 00051 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 00052 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 00053 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 00054 xtRegisterGroupState = 0x0010, /* States. */ 00055 00056 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 00057 xtRegisterGroupUser = 0x0200, /* User registers. */ 00058 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 00059 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 00060 xtRegisterGroupSystem = 0x1000, /* System. */ 00061 00062 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ 00063 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 00064 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 00065 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 00066 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 00067 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 00068 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 00069 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 00070 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 00071 00072 } xtensa_register_group_t; 00073 00074 00075 /* Xtensa target flags. */ 00076 00077 typedef enum 00078 { 00079 xtTargetFlagsNonVisibleRegs = 0x0001, 00080 xtTargetFlagsUseFetchStore = 0x0002, 00081 } xtensa_target_flags_t; 00082 00083 00084 /* Xtensa ELF core file register set representation ('.reg' section). 00085 Copied from target-side ELF header <xtensa/elf.h>. */ 00086 00087 typedef unsigned long xtensa_elf_greg_t; 00088 00089 typedef struct 00090 { 00091 xtensa_elf_greg_t pc; 00092 xtensa_elf_greg_t ps; 00093 xtensa_elf_greg_t lbeg; 00094 xtensa_elf_greg_t lend; 00095 xtensa_elf_greg_t lcount; 00096 xtensa_elf_greg_t sar; 00097 xtensa_elf_greg_t windowstart; 00098 xtensa_elf_greg_t windowbase; 00099 xtensa_elf_greg_t reserved[8+48]; 00100 xtensa_elf_greg_t ar[64]; 00101 } xtensa_elf_gregset_t; 00102 00103 #define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \ 00104 / sizeof (xtensa_elf_greg_t)) 00105 00106 /* Mask. */ 00107 00108 typedef struct 00109 { 00110 int reg_num; 00111 int bit_start; 00112 int bit_size; 00113 } xtensa_reg_mask_t; 00114 00115 typedef struct 00116 { 00117 int count; 00118 xtensa_reg_mask_t *mask; 00119 } xtensa_mask_t; 00120 00121 00122 /* Xtensa register representation. */ 00123 00124 typedef struct 00125 { 00126 char* name; /* Register name. */ 00127 int offset; /* Offset. */ 00128 xtensa_register_type_t type; /* Register type. */ 00129 xtensa_register_group_t group;/* Register group. */ 00130 struct type* ctype; /* C-type. */ 00131 int bit_size; /* The actual bit size in the target. */ 00132 int byte_size; /* Actual space allocated in registers[]. */ 00133 int align; /* Alignment for this register. */ 00134 00135 unsigned int target_number; /* Register target number. */ 00136 00137 int flags; /* Flags. */ 00138 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ 00139 00140 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 00141 const char *fetch; /* Instruction sequence to fetch register. */ 00142 const char *store; /* Instruction sequence to store register. */ 00143 } xtensa_register_t; 00144 00145 /* For xtensa-config.c to expand to the structure above. */ 00146 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ 00147 {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \ 00148 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, 00149 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0}, 00150 00151 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 00152 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 00153 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 00154 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 00155 00156 /* Call-ABI for stack frame. */ 00157 00158 typedef enum 00159 { 00160 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 00161 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 00162 } call_abi_t; 00163 00164 00165 /* Xtensa-specific target dependencies. */ 00166 00167 struct gdbarch_tdep 00168 { 00169 unsigned int target_flags; 00170 00171 /* Spill location for TIE register files under ocd. */ 00172 00173 unsigned int spill_location; 00174 unsigned int spill_size; 00175 00176 char *unused; /* Placeholder for compatibility. */ 00177 call_abi_t call_abi; /* Calling convention. */ 00178 00179 /* CPU configuration. */ 00180 00181 unsigned int debug_interrupt_level; 00182 00183 unsigned int icache_line_bytes; 00184 unsigned int dcache_line_bytes; 00185 unsigned int dcache_writeback; 00186 00187 unsigned int isa_use_windowed_registers; 00188 unsigned int isa_use_density_instructions; 00189 unsigned int isa_use_exceptions; 00190 unsigned int isa_use_ext_l32r; 00191 unsigned int isa_max_insn_size; /* Maximum instruction length. */ 00192 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ 00193 unsigned int debug_num_dbreaks; 00194 00195 /* Register map. */ 00196 00197 xtensa_register_t* regmap; 00198 00199 unsigned int num_regs; /* Number of registers in register map. */ 00200 unsigned int num_nopriv_regs; /* Number of non-privileged registers. */ 00201 unsigned int num_pseudo_regs; /* Number of pseudo registers. */ 00202 unsigned int num_aregs; /* Size of register file. */ 00203 unsigned int num_contexts; 00204 00205 int ar_base; /* Register number for AR0. */ 00206 int a0_base; /* Register number for A0 (pseudo). */ 00207 int wb_regnum; /* Register number for WB. */ 00208 int ws_regnum; /* Register number for WS. */ 00209 int pc_regnum; /* Register number for PC. */ 00210 int ps_regnum; /* Register number for PS. */ 00211 int lbeg_regnum; /* Register numbers for count regs. */ 00212 int lend_regnum; 00213 int lcount_regnum; 00214 int sar_regnum; /* Register number of SAR. */ 00215 int litbase_regnum; /* Register number of LITBASE. */ 00216 00217 int interrupt_regnum; /* Register number for interrupt. */ 00218 int interrupt2_regnum; /* Register number for interrupt2. */ 00219 int cpenable_regnum; /* Register number for cpenable. */ 00220 int debugcause_regnum; /* Register number for debugcause. */ 00221 int exccause_regnum; /* Register number for exccause. */ 00222 int excvaddr_regnum; /* Register number for excvaddr. */ 00223 00224 int max_register_raw_size; 00225 int max_register_virtual_size; 00226 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ 00227 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ 00228 unsigned long *gregmap; 00229 00230 /* Cached register types. */ 00231 struct ctype_cache 00232 { 00233 struct ctype_cache *next; 00234 int size; 00235 struct type *virtual_type; 00236 } *type_entries; 00237 }; 00238 00239 /* Macro to instantiate a gdbarch_tdep structure. */ 00240 00241 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ 00242 { \ 00243 .target_flags = 0, \ 00244 .spill_location = -1, \ 00245 .spill_size = (spillsz), \ 00246 .unused = 0, \ 00247 .call_abi = 0, \ 00248 .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ 00249 .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ 00250 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ 00251 .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \ 00252 .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \ 00253 .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \ 00254 .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \ 00255 .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \ 00256 .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ 00257 .debug_num_ibreaks = XCHAL_NUM_IBREAK, \ 00258 .debug_num_dbreaks = XCHAL_NUM_DBREAK, \ 00259 .regmap = rmap, \ 00260 .num_regs = 0, \ 00261 .num_nopriv_regs = 0, \ 00262 .num_pseudo_regs = 0, \ 00263 .num_aregs = XCHAL_NUM_AREGS, \ 00264 .num_contexts = XCHAL_NUM_CONTEXTS, \ 00265 .ar_base = -1, \ 00266 .a0_base = -1, \ 00267 .wb_regnum = -1, \ 00268 .ws_regnum = -1, \ 00269 .pc_regnum = -1, \ 00270 .ps_regnum = -1, \ 00271 .lbeg_regnum = -1, \ 00272 .lend_regnum = -1, \ 00273 .lcount_regnum = -1, \ 00274 .sar_regnum = -1, \ 00275 .litbase_regnum = -1, \ 00276 .interrupt_regnum = -1, \ 00277 .interrupt2_regnum = -1, \ 00278 .cpenable_regnum = -1, \ 00279 .debugcause_regnum = -1, \ 00280 .exccause_regnum = -1, \ 00281 .excvaddr_regnum = -1, \ 00282 .max_register_raw_size = 0, \ 00283 .max_register_virtual_size = 0, \ 00284 .fp_layout = 0, \ 00285 .fp_layout_bytes = 0, \ 00286 .gregmap = 0, \ 00287 } 00288 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ 00289 struct gdbarch_tdep xtensa_tdep = \ 00290 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); 00291 00292 #ifndef XCHAL_NUM_CONTEXTS 00293 #define XCHAL_NUM_CONTEXTS 0 00294 #endif 00295 #ifndef XCHAL_HAVE_EXCEPTIONS 00296 #define XCHAL_HAVE_EXCEPTIONS 1 00297 #endif 00298 #define WB_SHIFT 2 00299 00300 /* We assign fixed numbers to the registers of the "current" window 00301 (i.e., relative to WB). The registers get remapped via the reg_map 00302 data structure to their corresponding register in the AR register 00303 file (see xtensa-tdep.c). */ 00304
1.7.6.1
