|
GDB (API)
|
|
GDB (API)
|
00001 /* Target-dependent code for GDB, the GNU debugger. 00002 00003 Copyright (C) 2000-2013 Free Software Foundation, Inc. 00004 00005 This file is part of GDB. 00006 00007 This program is free software; you can redistribute it and/or modify 00008 it under the terms of the GNU General Public License as published by 00009 the Free Software Foundation; either version 3 of the License, or 00010 (at your option) any later version. 00011 00012 This program is distributed in the hope that it will be useful, 00013 but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 GNU General Public License for more details. 00016 00017 You should have received a copy of the GNU General Public License 00018 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 00019 00020 #ifndef PPC_TDEP_H 00021 #define PPC_TDEP_H 00022 00023 struct gdbarch; 00024 struct frame_info; 00025 struct value; 00026 struct regcache; 00027 struct type; 00028 00029 /* From ppc-sysv-tdep.c ... */ 00030 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch, 00031 struct value *function, 00032 struct type *valtype, 00033 struct regcache *regcache, 00034 gdb_byte *readbuf, 00035 const gdb_byte *writebuf); 00036 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch, 00037 struct value *function, 00038 struct type *valtype, 00039 struct regcache *regcache, 00040 gdb_byte *readbuf, 00041 const gdb_byte *writebuf); 00042 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, 00043 struct value *function, 00044 struct regcache *regcache, 00045 CORE_ADDR bp_addr, int nargs, 00046 struct value **args, CORE_ADDR sp, 00047 int struct_return, 00048 CORE_ADDR struct_addr); 00049 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, 00050 struct value *function, 00051 struct regcache *regcache, 00052 CORE_ADDR bp_addr, int nargs, 00053 struct value **args, CORE_ADDR sp, 00054 int struct_return, 00055 CORE_ADDR struct_addr); 00056 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, 00057 struct value *function, 00058 struct type *valtype, 00059 struct regcache *regcache, 00060 gdb_byte *readbuf, 00061 const gdb_byte *writebuf); 00062 00063 /* From rs6000-tdep.c... */ 00064 int altivec_register_p (struct gdbarch *gdbarch, int regno); 00065 int vsx_register_p (struct gdbarch *gdbarch, int regno); 00066 int spe_register_p (struct gdbarch *gdbarch, int regno); 00067 00068 /* Return non-zero if the architecture described by GDBARCH has 00069 floating-point registers (f0 --- f31 and fpscr). */ 00070 int ppc_floating_point_unit_p (struct gdbarch *gdbarch); 00071 00072 /* Return non-zero if the architecture described by GDBARCH has 00073 Altivec registers (vr0 --- vr31, vrsave and vscr). */ 00074 int ppc_altivec_support_p (struct gdbarch *gdbarch); 00075 00076 /* Return non-zero if the architecture described by GDBARCH has 00077 VSX registers (vsr0 --- vsr63). */ 00078 int vsx_support_p (struct gdbarch *gdbarch); 00079 int ppc_deal_with_atomic_sequence (struct frame_info *frame); 00080 00081 00082 /* Register set description. */ 00083 00084 struct ppc_reg_offsets 00085 { 00086 /* General-purpose registers. */ 00087 int r0_offset; 00088 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */ 00089 int xr_size; /* size for cr, xer, mq. */ 00090 int pc_offset; 00091 int ps_offset; 00092 int cr_offset; 00093 int lr_offset; 00094 int ctr_offset; 00095 int xer_offset; 00096 int mq_offset; 00097 00098 /* Floating-point registers. */ 00099 int f0_offset; 00100 int fpscr_offset; 00101 int fpscr_size; 00102 00103 /* AltiVec registers. */ 00104 int vr0_offset; 00105 int vscr_offset; 00106 int vrsave_offset; 00107 }; 00108 00109 extern void ppc_supply_reg (struct regcache *regcache, int regnum, 00110 const gdb_byte *regs, size_t offset, int regsize); 00111 00112 extern void ppc_collect_reg (const struct regcache *regcache, int regnum, 00113 gdb_byte *regs, size_t offset, int regsize); 00114 00115 /* Supply register REGNUM in the general-purpose register set REGSET 00116 from the buffer specified by GREGS and LEN to register cache 00117 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 00118 00119 extern void ppc_supply_gregset (const struct regset *regset, 00120 struct regcache *regcache, 00121 int regnum, const void *gregs, size_t len); 00122 00123 /* Supply register REGNUM in the floating-point register set REGSET 00124 from the buffer specified by FPREGS and LEN to register cache 00125 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 00126 00127 extern void ppc_supply_fpregset (const struct regset *regset, 00128 struct regcache *regcache, 00129 int regnum, const void *fpregs, size_t len); 00130 00131 /* Supply register REGNUM in the Altivec register set REGSET 00132 from the buffer specified by VRREGS and LEN to register cache 00133 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 00134 00135 extern void ppc_supply_vrregset (const struct regset *regset, 00136 struct regcache *regcache, 00137 int regnum, const void *vrregs, size_t len); 00138 00139 /* Supply register REGNUM in the VSX register set REGSET 00140 from the buffer specified by VSXREGS and LEN to register cache 00141 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 00142 00143 extern void ppc_supply_vsxregset (const struct regset *regset, 00144 struct regcache *regcache, 00145 int regnum, const void *vsxregs, size_t len); 00146 00147 /* Collect register REGNUM in the general-purpose register set 00148 REGSET, from register cache REGCACHE into the buffer specified by 00149 GREGS and LEN. If REGNUM is -1, do this for all registers in 00150 REGSET. */ 00151 00152 extern void ppc_collect_gregset (const struct regset *regset, 00153 const struct regcache *regcache, 00154 int regnum, void *gregs, size_t len); 00155 00156 /* Collect register REGNUM in the floating-point register set 00157 REGSET, from register cache REGCACHE into the buffer specified by 00158 FPREGS and LEN. If REGNUM is -1, do this for all registers in 00159 REGSET. */ 00160 00161 extern void ppc_collect_fpregset (const struct regset *regset, 00162 const struct regcache *regcache, 00163 int regnum, void *fpregs, size_t len); 00164 00165 /* Collect register REGNUM in the Altivec register set 00166 REGSET from register cache REGCACHE into the buffer specified by 00167 VRREGS and LEN. If REGNUM is -1, do this for all registers in 00168 REGSET. */ 00169 00170 extern void ppc_collect_vrregset (const struct regset *regset, 00171 const struct regcache *regcache, 00172 int regnum, void *vrregs, size_t len); 00173 00174 /* Collect register REGNUM in the VSX register set 00175 REGSET from register cache REGCACHE into the buffer specified by 00176 VSXREGS and LEN. If REGNUM is -1, do this for all registers in 00177 REGSET. */ 00178 00179 extern void ppc_collect_vsxregset (const struct regset *regset, 00180 const struct regcache *regcache, 00181 int regnum, void *vsxregs, size_t len); 00182 00183 /* Private data that this module attaches to struct gdbarch. */ 00184 00185 /* Vector ABI used by the inferior. */ 00186 enum powerpc_vector_abi 00187 { 00188 POWERPC_VEC_AUTO, 00189 POWERPC_VEC_GENERIC, 00190 POWERPC_VEC_ALTIVEC, 00191 POWERPC_VEC_SPE, 00192 POWERPC_VEC_LAST 00193 }; 00194 00195 struct gdbarch_tdep 00196 { 00197 int wordsize; /* Size in bytes of fixed-point word. */ 00198 int soft_float; /* Avoid FP registers for arguments? */ 00199 00200 /* How to pass vector arguments. Never set to AUTO or LAST. */ 00201 enum powerpc_vector_abi vector_abi; 00202 00203 int ppc_gp0_regnum; /* GPR register 0 */ 00204 int ppc_toc_regnum; /* TOC register */ 00205 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */ 00206 int ppc_cr_regnum; /* Condition register */ 00207 int ppc_lr_regnum; /* Link register */ 00208 int ppc_ctr_regnum; /* Count register */ 00209 int ppc_xer_regnum; /* Integer exception register */ 00210 00211 /* Not all PPC and RS6000 variants will have the registers 00212 represented below. A -1 is used to indicate that the register 00213 is not present in this variant. */ 00214 00215 /* Floating-point registers. */ 00216 int ppc_fp0_regnum; /* Floating-point register 0. */ 00217 int ppc_fpscr_regnum; /* fp status and condition register. */ 00218 00219 /* Multiplier-Quotient Register (older POWER architectures only). */ 00220 int ppc_mq_regnum; 00221 00222 /* POWER7 VSX registers. */ 00223 int ppc_vsr0_regnum; /* First VSX register. */ 00224 int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */ 00225 int ppc_efpr0_regnum; /* First Extended FP register. */ 00226 00227 /* Altivec registers. */ 00228 int ppc_vr0_regnum; /* First AltiVec register. */ 00229 int ppc_vrsave_regnum; /* Last AltiVec register. */ 00230 00231 /* SPE registers. */ 00232 int ppc_ev0_upper_regnum; /* First GPR upper half register. */ 00233 int ppc_ev0_regnum; /* First ev register. */ 00234 int ppc_acc_regnum; /* SPE 'acc' register. */ 00235 int ppc_spefscr_regnum; /* SPE 'spefscr' register. */ 00236 00237 /* Decimal 128 registers. */ 00238 int ppc_dl0_regnum; /* First Decimal128 argument register pair. */ 00239 00240 /* Offset to ABI specific location where link register is saved. */ 00241 int lr_frame_offset; 00242 00243 /* An array of integers, such that sim_regno[I] is the simulator 00244 register number for GDB register number I, or -1 if the 00245 simulator does not implement that register. */ 00246 int *sim_regno; 00247 00248 /* ISA-specific types. */ 00249 struct type *ppc_builtin_type_vec64; 00250 struct type *ppc_builtin_type_vec128; 00251 }; 00252 00253 00254 /* Constants for register set sizes. */ 00255 enum 00256 { 00257 ppc_num_gprs = 32, /* 32 general-purpose registers. */ 00258 ppc_num_fprs = 32, /* 32 floating-point registers. */ 00259 ppc_num_srs = 16, /* 16 segment registers. */ 00260 ppc_num_vrs = 32, /* 32 Altivec vector registers. */ 00261 ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ 00262 ppc_num_vsrs = 64, /* 64 VSX vector registers. */ 00263 ppc_num_efprs = 32 /* 32 Extended FP registers. */ 00264 }; 00265 00266 00267 /* Register number constants. These are GDB internal register 00268 numbers; they are not used for the simulator or remote targets. 00269 Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given 00270 numbers above PPC_NUM_REGS. So are segment registers and other 00271 target-defined registers. */ 00272 enum { 00273 PPC_R0_REGNUM = 0, 00274 PPC_F0_REGNUM = 32, 00275 PPC_PC_REGNUM = 64, 00276 PPC_MSR_REGNUM = 65, 00277 PPC_CR_REGNUM = 66, 00278 PPC_LR_REGNUM = 67, 00279 PPC_CTR_REGNUM = 68, 00280 PPC_XER_REGNUM = 69, 00281 PPC_FPSCR_REGNUM = 70, 00282 PPC_MQ_REGNUM = 71, 00283 PPC_SPE_UPPER_GP0_REGNUM = 72, 00284 PPC_SPE_ACC_REGNUM = 104, 00285 PPC_SPE_FSCR_REGNUM = 105, 00286 PPC_VR0_REGNUM = 106, 00287 PPC_VSCR_REGNUM = 138, 00288 PPC_VRSAVE_REGNUM = 139, 00289 PPC_VSR0_UPPER_REGNUM = 140, 00290 PPC_VSR31_UPPER_REGNUM = 171, 00291 PPC_NUM_REGS 00292 }; 00293 00294 /* An instruction to match. */ 00295 00296 struct ppc_insn_pattern 00297 { 00298 unsigned int mask; /* mask the insn with this... */ 00299 unsigned int data; /* ...and see if it matches this. */ 00300 int optional; /* If non-zero, this insn may be absent. */ 00301 }; 00302 00303 extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, 00304 struct ppc_insn_pattern *pattern, 00305 unsigned int *insns); 00306 extern CORE_ADDR ppc_insn_d_field (unsigned int insn); 00307 00308 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn); 00309 00310 /* Instruction size. */ 00311 #define PPC_INSN_SIZE 4 00312 00313 /* Estimate for the maximum number of instrctions in a function epilogue. */ 00314 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52 00315 00316 #endif /* ppc-tdep.h */
1.7.6.1
