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/home/stan/gdb/src/gdb/mep-tdep.c
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00001 /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger.
00002 
00003    Copyright (C) 2001-2013 Free Software Foundation, Inc.
00004 
00005    Contributed by Red Hat, Inc.
00006 
00007    This file is part of GDB.
00008 
00009    This program is free software; you can redistribute it and/or modify
00010    it under the terms of the GNU General Public License as published by
00011    the Free Software Foundation; either version 3 of the License, or
00012    (at your option) any later version.
00013 
00014    This program is distributed in the hope that it will be useful,
00015    but WITHOUT ANY WARRANTY; without even the implied warranty of
00016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017    GNU General Public License for more details.
00018 
00019    You should have received a copy of the GNU General Public License
00020    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
00021 
00022 #include "defs.h"
00023 #include "frame.h"
00024 #include "frame-unwind.h"
00025 #include "frame-base.h"
00026 #include "symtab.h"
00027 #include "gdbtypes.h"
00028 #include "gdbcmd.h"
00029 #include "gdbcore.h"
00030 #include "gdb_string.h"
00031 #include "value.h"
00032 #include "inferior.h"
00033 #include "dis-asm.h"
00034 #include "symfile.h"
00035 #include "objfiles.h"
00036 #include "language.h"
00037 #include "arch-utils.h"
00038 #include "regcache.h"
00039 #include "remote.h"
00040 #include "floatformat.h"
00041 #include "sim-regno.h"
00042 #include "disasm.h"
00043 #include "trad-frame.h"
00044 #include "reggroups.h"
00045 #include "elf-bfd.h"
00046 #include "elf/mep.h"
00047 #include "prologue-value.h"
00048 #include "cgen/bitset.h"
00049 #include "infcall.h"
00050 
00051 #include "gdb_assert.h"
00052 
00053 /* Get the user's customized MeP coprocessor register names from
00054    libopcodes.  */
00055 #include "opcodes/mep-desc.h"
00056 #include "opcodes/mep-opc.h"
00057 
00058 
00059 /* The gdbarch_tdep structure.  */
00060 
00061 /* A quick recap for GDB hackers not familiar with the whole Toshiba
00062    Media Processor story:
00063 
00064    The MeP media engine is a configureable processor: users can design
00065    their own coprocessors, implement custom instructions, adjust cache
00066    sizes, select optional standard facilities like add-and-saturate
00067    instructions, and so on.  Then, they can build custom versions of
00068    the GNU toolchain to support their customized chips.  The
00069    MeP-Integrator program (see utils/mep) takes a GNU toolchain source
00070    tree, and a config file pointing to various files provided by the
00071    user describing their customizations, and edits the source tree to
00072    produce a compiler that can generate their custom instructions, an
00073    assembler that can assemble them and recognize their custom
00074    register names, and so on.
00075 
00076    Furthermore, the user can actually specify several of these custom
00077    configurations, called 'me_modules', and get a toolchain which can
00078    produce code for any of them, given a compiler/assembler switch;
00079    you say something like 'gcc -mconfig=mm_max' to generate code for
00080    the me_module named 'mm_max'.
00081 
00082    GDB, in particular, needs to:
00083 
00084    - use the coprocessor control register names provided by the user
00085      in their hardware description, in expressions, 'info register'
00086      output, and disassembly,
00087 
00088    - know the number, names, and types of the coprocessor's
00089      general-purpose registers, adjust the 'info all-registers' output
00090      accordingly, and print error messages if the user refers to one
00091      that doesn't exist
00092 
00093    - allow access to the control bus space only when the configuration
00094      actually has a control bus, and recognize which regions of the
00095      control bus space are actually populated,
00096 
00097    - disassemble using the user's provided mnemonics for their custom
00098      instructions, and
00099 
00100    - recognize whether the $hi and $lo registers are present, and
00101      allow access to them only when they are actually there.
00102 
00103    There are three sources of information about what sort of me_module
00104    we're actually dealing with:
00105 
00106    - A MeP executable file indicates which me_module it was compiled
00107      for, and libopcodes has tables describing each module.  So, given
00108      an executable file, we can find out about the processor it was
00109      compiled for.
00110 
00111    - There are SID command-line options to select a particular
00112      me_module, overriding the one specified in the ELF file.  SID
00113      provides GDB with a fake read-only register, 'module', which
00114      indicates which me_module GDB is communicating with an instance
00115      of.
00116 
00117    - There are SID command-line options to enable or disable certain
00118      optional processor features, overriding the defaults for the
00119      selected me_module.  The MeP $OPT register indicates which
00120      options are present on the current processor.  */
00121 
00122 
00123 struct gdbarch_tdep
00124 {
00125   /* A CGEN cpu descriptor for this BFD architecture and machine.
00126 
00127      Note: this is *not* customized for any particular me_module; the
00128      MeP libopcodes machinery actually puts off module-specific
00129      customization until the last minute.  So this contains
00130      information about all supported me_modules.  */
00131   CGEN_CPU_DESC cpu_desc;
00132 
00133   /* The me_module index from the ELF file we used to select this
00134      architecture, or CONFIG_NONE if there was none.
00135 
00136      Note that we should prefer to use the me_module number available
00137      via the 'module' register, whenever we're actually talking to a
00138      real target.
00139 
00140      In the absence of live information, we'd like to get the
00141      me_module number from the ELF file.  But which ELF file: the
00142      executable file, the core file, ... ?  The answer is, "the last
00143      ELF file we used to set the current architecture".  Thus, we
00144      create a separate instance of the gdbarch structure for each
00145      me_module value mep_gdbarch_init sees, and store the me_module
00146      value from the ELF file here.  */
00147   CONFIG_ATTR me_module;
00148 };
00149 
00150 
00151 
00152 /* Getting me_module information from the CGEN tables.  */
00153 
00154 
00155 /* Find an entry in the DESC's hardware table whose name begins with
00156    PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not
00157    intersect with GENERIC_ISA_MASK.  If there is no matching entry,
00158    return zero.  */
00159 static const CGEN_HW_ENTRY *
00160 find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc,
00161                                  const char *prefix,
00162                                  CGEN_BITSET *copro_isa_mask,
00163                                  CGEN_BITSET *generic_isa_mask)
00164 {
00165   int prefix_len = strlen (prefix);
00166   int i;
00167 
00168   for (i = 0; i < desc->hw_table.num_entries; i++)
00169     {
00170       const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
00171       if (strncmp (prefix, hw->name, prefix_len) == 0)
00172         {
00173           CGEN_BITSET *hw_isa_mask
00174             = ((CGEN_BITSET *)
00175                &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw)));
00176 
00177           if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask)
00178               && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask))
00179             return hw;
00180         }
00181     }
00182 
00183   return 0;
00184 }
00185 
00186 
00187 /* Find an entry in DESC's hardware table whose type is TYPE.  Return
00188    zero if there is none.  */
00189 static const CGEN_HW_ENTRY *
00190 find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type)
00191 {
00192   int i;
00193 
00194   for (i = 0; i < desc->hw_table.num_entries; i++)
00195     {
00196       const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i];
00197 
00198       if (hw->type == type)
00199         return hw;
00200     }
00201 
00202   return 0;
00203 }
00204 
00205 
00206 /* Return the CGEN hardware table entry for the coprocessor register
00207    set for ME_MODULE, whose name prefix is PREFIX.  If ME_MODULE has
00208    no such register set, return zero.  If ME_MODULE is the generic
00209    me_module CONFIG_NONE, return the table entry for the register set
00210    whose hardware type is GENERIC_TYPE.  */
00211 static const CGEN_HW_ENTRY *
00212 me_module_register_set (CONFIG_ATTR me_module,
00213                         const char *prefix,
00214                         CGEN_HW_TYPE generic_type)
00215 {
00216   /* This is kind of tricky, because the hardware table is constructed
00217      in a way that isn't very helpful.  Perhaps we can fix that, but
00218      here's how it works at the moment:
00219 
00220      The configuration map, `mep_config_map', is indexed by me_module
00221      number, and indicates which coprocessor and core ISAs that
00222      me_module supports.  The 'core_isa' mask includes all the core
00223      ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs.
00224      The entry for the generic me_module, CONFIG_NONE, has an empty
00225      'cop_isa', and its 'core_isa' selects only the standard MeP
00226      instruction set.
00227 
00228      The CGEN CPU descriptor's hardware table, desc->hw_table, has
00229      entries for all the register sets, for all me_modules.  Each
00230      entry has a mask indicating which ISAs use that register set.
00231      So, if an me_module supports some coprocessor ISA, we can find
00232      applicable register sets by scanning the hardware table for
00233      register sets whose masks include (at least some of) those ISAs.
00234 
00235      Each hardware table entry also has a name, whose prefix says
00236      whether it's a general-purpose ("h-cr") or control ("h-ccr")
00237      coprocessor register set.  It might be nicer to have an attribute
00238      indicating what sort of register set it was, that we could use
00239      instead of pattern-matching on the name.
00240 
00241      When there is no hardware table entry whose mask includes a
00242      particular coprocessor ISA and whose name starts with a given
00243      prefix, then that means that that coprocessor doesn't have any
00244      registers of that type.  In such cases, this function must return
00245      a null pointer.
00246 
00247      Coprocessor register sets' masks may or may not include the core
00248      ISA for the me_module they belong to.  Those generated by a2cgen
00249      do, but the sample me_module included in the unconfigured tree,
00250      'ccfx', does not.
00251 
00252      There are generic coprocessor register sets, intended only for
00253      use with the generic me_module.  Unfortunately, their masks
00254      include *all* ISAs --- even those for coprocessors that don't
00255      have such register sets.  This makes detecting the case where a
00256      coprocessor lacks a particular register set more complicated.
00257 
00258      So, here's the approach we take:
00259 
00260      - For CONFIG_NONE, we return the generic coprocessor register set.
00261 
00262      - For any other me_module, we search for a register set whose
00263        mask contains any of the me_module's coprocessor ISAs,
00264        specifically excluding the generic coprocessor register sets.  */
00265 
00266   CGEN_CPU_DESC desc = gdbarch_tdep (target_gdbarch ())->cpu_desc;
00267   const CGEN_HW_ENTRY *hw;
00268 
00269   if (me_module == CONFIG_NONE)
00270     hw = find_hw_entry_by_type (desc, generic_type);
00271   else
00272     {
00273       CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa;
00274       CGEN_BITSET *core = &mep_config_map[me_module].core_isa;
00275       CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa;
00276       CGEN_BITSET *cop_and_core;
00277 
00278       /* The coprocessor ISAs include the ISA for the specific core which
00279          has that coprocessor.  */
00280       cop_and_core = cgen_bitset_copy (cop);
00281       cgen_bitset_union (cop, core, cop_and_core);
00282       hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic);
00283     }
00284 
00285   return hw;
00286 }
00287 
00288 
00289 /* Given a hardware table entry HW representing a register set, return
00290    a pointer to the keyword table with all the register names.  If HW
00291    is NULL, return NULL, to propage the "no such register set" info
00292    along.  */
00293 static CGEN_KEYWORD *
00294 register_set_keyword_table (const CGEN_HW_ENTRY *hw)
00295 {
00296   if (! hw)
00297     return NULL;
00298 
00299   /* Check that HW is actually a keyword table.  */
00300   gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD);
00301 
00302   /* The 'asm_data' field of a register set's hardware table entry
00303      refers to a keyword table.  */
00304   return (CGEN_KEYWORD *) hw->asm_data;
00305 }
00306 
00307 
00308 /* Given a keyword table KEYWORD and a register number REGNUM, return
00309    the name of the register, or "" if KEYWORD contains no register
00310    whose number is REGNUM.  */
00311 static char *
00312 register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum)
00313 {
00314   const CGEN_KEYWORD_ENTRY *entry
00315     = cgen_keyword_lookup_value (keyword_table, regnum);
00316 
00317   if (entry)
00318     {
00319       char *name = entry->name;
00320 
00321       /* The CGEN keyword entries for register names include the
00322          leading $, which appears in MeP assembly as well as in GDB.
00323          But we don't want to return that; GDB core code adds that
00324          itself.  */
00325       if (name[0] == '$')
00326         name++;
00327 
00328       return name;
00329     }
00330   else
00331     return "";
00332 }
00333 
00334   
00335 /* Masks for option bits in the OPT special-purpose register.  */
00336 enum {
00337   MEP_OPT_DIV = 1 << 25,        /* 32-bit divide instruction option */
00338   MEP_OPT_MUL = 1 << 24,        /* 32-bit multiply instruction option */
00339   MEP_OPT_BIT = 1 << 23,        /* bit manipulation instruction option */
00340   MEP_OPT_SAT = 1 << 22,        /* saturation instruction option */
00341   MEP_OPT_CLP = 1 << 21,        /* clip instruction option */
00342   MEP_OPT_MIN = 1 << 20,        /* min/max instruction option */
00343   MEP_OPT_AVE = 1 << 19,        /* average instruction option */
00344   MEP_OPT_ABS = 1 << 18,        /* absolute difference instruction option */
00345   MEP_OPT_LDZ = 1 << 16,        /* leading zero instruction option */
00346   MEP_OPT_VL64 = 1 << 6,        /* 64-bit VLIW operation mode option */
00347   MEP_OPT_VL32 = 1 << 5,        /* 32-bit VLIW operation mode option */
00348   MEP_OPT_COP = 1 << 4,         /* coprocessor option */
00349   MEP_OPT_DSP = 1 << 2,         /* DSP option */
00350   MEP_OPT_UCI = 1 << 1,         /* UCI option */
00351   MEP_OPT_DBG = 1 << 0,         /* DBG function option */
00352 };
00353 
00354 
00355 /* Given the option_mask value for a particular entry in
00356    mep_config_map, produce the value the processor's OPT register
00357    would use to represent the same set of options.  */
00358 static unsigned int
00359 opt_from_option_mask (unsigned int option_mask)
00360 {
00361   /* A table mapping OPT register bits onto CGEN config map option
00362      bits.  */
00363   struct {
00364     unsigned int opt_bit, option_mask_bit;
00365   } bits[] = {
00366     { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
00367     { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN },
00368     { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN },
00369     { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN },
00370     { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN },
00371     { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN },
00372     { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN },
00373     { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN },
00374     { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN },
00375     { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN },
00376     { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN },
00377     { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN },
00378     { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN },
00379   };
00380 
00381   int i;
00382   unsigned int opt = 0;
00383 
00384   for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++)
00385     if (option_mask & bits[i].option_mask_bit)
00386       opt |= bits[i].opt_bit;
00387 
00388   return opt;
00389 }
00390 
00391 
00392 /* Return the value the $OPT register would use to represent the set
00393    of options for ME_MODULE.  */
00394 static unsigned int
00395 me_module_opt (CONFIG_ATTR me_module)
00396 {
00397   return opt_from_option_mask (mep_config_map[me_module].option_mask);
00398 }
00399 
00400 
00401 /* Return the width of ME_MODULE's coprocessor data bus, in bits.
00402    This is either 32 or 64.  */
00403 static int
00404 me_module_cop_data_bus_width (CONFIG_ATTR me_module)
00405 {
00406   if (mep_config_map[me_module].option_mask
00407       & (1 << CGEN_INSN_OPTIONAL_CP64_INSN))
00408     return 64;
00409   else
00410     return 32;
00411 }
00412 
00413 
00414 /* Return true if ME_MODULE is big-endian, false otherwise.  */
00415 static int
00416 me_module_big_endian (CONFIG_ATTR me_module)
00417 {
00418   return mep_config_map[me_module].big_endian;
00419 }
00420 
00421 
00422 /* Return the name of ME_MODULE, or NULL if it has no name.  */
00423 static const char *
00424 me_module_name (CONFIG_ATTR me_module)
00425 {
00426   /* The default me_module has "" as its name, but it's easier for our
00427      callers to test for NULL.  */
00428   if (! mep_config_map[me_module].name
00429       || mep_config_map[me_module].name[0] == '\0')
00430     return NULL;
00431   else
00432     return mep_config_map[me_module].name;
00433 }
00434 
00435 /* Register set.  */
00436 
00437 
00438 /* The MeP spec defines the following registers:
00439    16 general purpose registers (r0-r15) 
00440    32 control/special registers (csr0-csr31)
00441    32 coprocessor general-purpose registers (c0 -- c31)
00442    64 coprocessor control registers (ccr0 -- ccr63)
00443 
00444    For the raw registers, we assign numbers here explicitly, instead
00445    of letting the enum assign them for us; the numbers are a matter of
00446    external protocol, and shouldn't shift around as things are edited.
00447 
00448    We access the control/special registers via pseudoregisters, to
00449    enforce read-only portions that some registers have.
00450 
00451    We access the coprocessor general purpose and control registers via
00452    pseudoregisters, to make sure they appear in the proper order in
00453    the 'info all-registers' command (which uses the register number
00454    ordering), and also to allow them to be renamed and resized
00455    depending on the me_module in use.
00456 
00457    The MeP allows coprocessor general-purpose registers to be either
00458    32 or 64 bits long, depending on the configuration.  Since we don't
00459    want the format of the 'g' packet to vary from one core to another,
00460    the raw coprocessor GPRs are always 64 bits.  GDB doesn't allow the
00461    types of registers to change (see the implementation of
00462    register_type), so we have four banks of pseudoregisters for the
00463    coprocessor gprs --- 32-bit vs. 64-bit, and integer
00464    vs. floating-point --- and we show or hide them depending on the
00465    configuration.  */
00466 enum
00467 {
00468   MEP_FIRST_RAW_REGNUM = 0,
00469 
00470   MEP_FIRST_GPR_REGNUM = 0,
00471   MEP_R0_REGNUM = 0,
00472   MEP_R1_REGNUM = 1,
00473   MEP_R2_REGNUM = 2,
00474   MEP_R3_REGNUM = 3,
00475   MEP_R4_REGNUM = 4,
00476   MEP_R5_REGNUM = 5,
00477   MEP_R6_REGNUM = 6,
00478   MEP_R7_REGNUM = 7,
00479   MEP_R8_REGNUM = 8,
00480   MEP_R9_REGNUM = 9,
00481   MEP_R10_REGNUM = 10,
00482   MEP_R11_REGNUM = 11,
00483   MEP_R12_REGNUM = 12,
00484   MEP_FP_REGNUM = MEP_R8_REGNUM,
00485   MEP_R13_REGNUM = 13,
00486   MEP_TP_REGNUM = MEP_R13_REGNUM,       /* (r13) Tiny data pointer */
00487   MEP_R14_REGNUM = 14,
00488   MEP_GP_REGNUM = MEP_R14_REGNUM,       /* (r14) Global pointer */
00489   MEP_R15_REGNUM = 15,
00490   MEP_SP_REGNUM = MEP_R15_REGNUM,       /* (r15) Stack pointer */
00491   MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM,
00492 
00493   /* The raw control registers.  These are the values as received via
00494      the remote protocol, directly from the target; we only let user
00495      code touch the via the pseudoregisters, which enforce read-only
00496      bits.  */
00497   MEP_FIRST_RAW_CSR_REGNUM = 16,
00498   MEP_RAW_PC_REGNUM    = 16,    /* Program counter */
00499   MEP_RAW_LP_REGNUM    = 17,    /* Link pointer */
00500   MEP_RAW_SAR_REGNUM   = 18,    /* Raw shift amount */
00501   MEP_RAW_CSR3_REGNUM  = 19,    /* csr3: reserved */
00502   MEP_RAW_RPB_REGNUM   = 20,    /* Raw repeat begin address */
00503   MEP_RAW_RPE_REGNUM   = 21,    /* Repeat end address */
00504   MEP_RAW_RPC_REGNUM   = 22,    /* Repeat count */
00505   MEP_RAW_HI_REGNUM    = 23, /* Upper 32 bits of result of 64 bit mult/div */
00506   MEP_RAW_LO_REGNUM    = 24, /* Lower 32 bits of result of 64 bit mult/div */
00507   MEP_RAW_CSR9_REGNUM  = 25,    /* csr3: reserved */
00508   MEP_RAW_CSR10_REGNUM = 26,    /* csr3: reserved */
00509   MEP_RAW_CSR11_REGNUM = 27,    /* csr3: reserved */
00510   MEP_RAW_MB0_REGNUM   = 28,    /* Raw modulo begin address 0 */
00511   MEP_RAW_ME0_REGNUM   = 29,    /* Raw modulo end address 0 */
00512   MEP_RAW_MB1_REGNUM   = 30,    /* Raw modulo begin address 1 */
00513   MEP_RAW_ME1_REGNUM   = 31,    /* Raw modulo end address 1 */
00514   MEP_RAW_PSW_REGNUM   = 32,    /* Raw program status word */
00515   MEP_RAW_ID_REGNUM    = 33,    /* Raw processor ID/revision */
00516   MEP_RAW_TMP_REGNUM   = 34,    /* Temporary */
00517   MEP_RAW_EPC_REGNUM   = 35,    /* Exception program counter */
00518   MEP_RAW_EXC_REGNUM   = 36,    /* Raw exception cause */
00519   MEP_RAW_CFG_REGNUM   = 37,    /* Raw processor configuration*/
00520   MEP_RAW_CSR22_REGNUM = 38,    /* csr3: reserved */
00521   MEP_RAW_NPC_REGNUM   = 39,    /* Nonmaskable interrupt PC */
00522   MEP_RAW_DBG_REGNUM   = 40,    /* Raw debug */
00523   MEP_RAW_DEPC_REGNUM  = 41,    /* Debug exception PC */
00524   MEP_RAW_OPT_REGNUM   = 42,    /* Raw options */
00525   MEP_RAW_RCFG_REGNUM  = 43,    /* Raw local ram config */
00526   MEP_RAW_CCFG_REGNUM  = 44,    /* Raw cache config */
00527   MEP_RAW_CSR29_REGNUM = 45,    /* csr3: reserved */
00528   MEP_RAW_CSR30_REGNUM = 46,    /* csr3: reserved */
00529   MEP_RAW_CSR31_REGNUM = 47,    /* csr3: reserved */
00530   MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM,
00531 
00532   /* The raw coprocessor general-purpose registers.  These are all 64
00533      bits wide.  */
00534   MEP_FIRST_RAW_CR_REGNUM = 48,
00535   MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31,
00536 
00537   MEP_FIRST_RAW_CCR_REGNUM = 80,
00538   MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63,
00539 
00540   /* The module number register.  This is the index of the me_module
00541      of which the current target is an instance.  (This is not a real
00542      MeP-specified register; it's provided by SID.)  */
00543   MEP_MODULE_REGNUM,
00544 
00545   MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM,
00546 
00547   MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1,
00548 
00549   /* Pseudoregisters.  See mep_pseudo_register_read and
00550      mep_pseudo_register_write.  */
00551   MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS,
00552 
00553   /* We have a pseudoregister for every control/special register, to
00554      implement registers with read-only bits.  */
00555   MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM,
00556   MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */
00557   MEP_LP_REGNUM,                /* Link pointer */
00558   MEP_SAR_REGNUM,               /* shift amount */
00559   MEP_CSR3_REGNUM,              /* csr3: reserved */
00560   MEP_RPB_REGNUM,               /* repeat begin address */
00561   MEP_RPE_REGNUM,               /* Repeat end address */
00562   MEP_RPC_REGNUM,               /* Repeat count */
00563   MEP_HI_REGNUM,  /* Upper 32 bits of the result of 64 bit mult/div */
00564   MEP_LO_REGNUM,  /* Lower 32 bits of the result of 64 bit mult/div */
00565   MEP_CSR9_REGNUM,              /* csr3: reserved */
00566   MEP_CSR10_REGNUM,             /* csr3: reserved */
00567   MEP_CSR11_REGNUM,             /* csr3: reserved */
00568   MEP_MB0_REGNUM,               /* modulo begin address 0 */
00569   MEP_ME0_REGNUM,               /* modulo end address 0 */
00570   MEP_MB1_REGNUM,               /* modulo begin address 1 */
00571   MEP_ME1_REGNUM,               /* modulo end address 1 */
00572   MEP_PSW_REGNUM,               /* program status word */
00573   MEP_ID_REGNUM,                /* processor ID/revision */
00574   MEP_TMP_REGNUM,               /* Temporary */
00575   MEP_EPC_REGNUM,               /* Exception program counter */
00576   MEP_EXC_REGNUM,               /* exception cause */
00577   MEP_CFG_REGNUM,               /* processor configuration*/
00578   MEP_CSR22_REGNUM,             /* csr3: reserved */
00579   MEP_NPC_REGNUM,               /* Nonmaskable interrupt PC */
00580   MEP_DBG_REGNUM,               /* debug */
00581   MEP_DEPC_REGNUM,              /* Debug exception PC */
00582   MEP_OPT_REGNUM,               /* options */
00583   MEP_RCFG_REGNUM,              /* local ram config */
00584   MEP_CCFG_REGNUM,              /* cache config */
00585   MEP_CSR29_REGNUM,             /* csr3: reserved */
00586   MEP_CSR30_REGNUM,             /* csr3: reserved */
00587   MEP_CSR31_REGNUM,             /* csr3: reserved */
00588   MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM,
00589 
00590   /* The 32-bit integer view of the coprocessor GPR's.  */
00591   MEP_FIRST_CR32_REGNUM,
00592   MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31,
00593 
00594   /* The 32-bit floating-point view of the coprocessor GPR's.  */
00595   MEP_FIRST_FP_CR32_REGNUM,
00596   MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31,
00597 
00598   /* The 64-bit integer view of the coprocessor GPR's.  */
00599   MEP_FIRST_CR64_REGNUM,
00600   MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31,
00601 
00602   /* The 64-bit floating-point view of the coprocessor GPR's.  */
00603   MEP_FIRST_FP_CR64_REGNUM,
00604   MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31,
00605 
00606   MEP_FIRST_CCR_REGNUM,
00607   MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63,
00608 
00609   MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM,
00610 
00611   MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM),
00612 
00613   MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS
00614 };
00615 
00616 
00617 #define IN_SET(set, n) \
00618   (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM)
00619 
00620 #define IS_GPR_REGNUM(n)     (IN_SET (GPR,     (n)))
00621 #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n)))
00622 #define IS_RAW_CR_REGNUM(n)  (IN_SET (RAW_CR,  (n)))
00623 #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n)))
00624 
00625 #define IS_CSR_REGNUM(n)     (IN_SET (CSR,     (n)))
00626 #define IS_CR32_REGNUM(n)    (IN_SET (CR32,    (n)))
00627 #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n)))
00628 #define IS_CR64_REGNUM(n)    (IN_SET (CR64,    (n)))
00629 #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n)))
00630 #define IS_CR_REGNUM(n)      (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \
00631                               || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n))
00632 #define IS_CCR_REGNUM(n)     (IN_SET (CCR,     (n)))
00633 
00634 #define IS_RAW_REGNUM(n)     (IN_SET (RAW,     (n)))
00635 #define IS_PSEUDO_REGNUM(n)  (IN_SET (PSEUDO,  (n)))
00636 
00637 #define NUM_REGS_IN_SET(set) \
00638   (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1)
00639 
00640 #define MEP_GPR_SIZE (4)        /* Size of a MeP general-purpose register.  */
00641 #define MEP_PSW_SIZE (4)        /* Size of the PSW register.  */
00642 #define MEP_LP_SIZE (4)         /* Size of the LP register.  */
00643 
00644 
00645 /* Many of the control/special registers contain bits that cannot be
00646    written to; some are entirely read-only.  So we present them all as
00647    pseudoregisters.
00648 
00649    The following table describes the special properties of each CSR.  */
00650 struct mep_csr_register
00651 {
00652   /* The number of this CSR's raw register.  */
00653   int raw;
00654 
00655   /* The number of this CSR's pseudoregister.  */
00656   int pseudo;
00657 
00658   /* A mask of the bits that are writeable: if a bit is set here, then
00659      it can be modified; if the bit is clear, then it cannot.  */
00660   LONGEST writeable_bits;
00661 };
00662 
00663 
00664 /* mep_csr_registers[i] describes the i'th CSR.
00665    We just list the register numbers here explicitly to help catch
00666    typos.  */
00667 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
00668 struct mep_csr_register mep_csr_registers[] = {
00669   { CSR(PC),    0xffffffff },   /* manual says r/o, but we can write it */
00670   { CSR(LP),    0xffffffff },
00671   { CSR(SAR),   0x0000003f },
00672   { CSR(CSR3),  0xffffffff },
00673   { CSR(RPB),   0xfffffffe },
00674   { CSR(RPE),   0xffffffff },
00675   { CSR(RPC),   0xffffffff },
00676   { CSR(HI),    0xffffffff },
00677   { CSR(LO),    0xffffffff },
00678   { CSR(CSR9),  0xffffffff },
00679   { CSR(CSR10), 0xffffffff },
00680   { CSR(CSR11), 0xffffffff },
00681   { CSR(MB0),   0x0000ffff },
00682   { CSR(ME0),   0x0000ffff },
00683   { CSR(MB1),   0x0000ffff },
00684   { CSR(ME1),   0x0000ffff },
00685   { CSR(PSW),   0x000003ff },
00686   { CSR(ID),    0x00000000 },
00687   { CSR(TMP),   0xffffffff },
00688   { CSR(EPC),   0xffffffff },
00689   { CSR(EXC),   0x000030f0 },
00690   { CSR(CFG),   0x00c0001b },
00691   { CSR(CSR22), 0xffffffff },
00692   { CSR(NPC),   0xffffffff },
00693   { CSR(DBG),   0x00000580 },
00694   { CSR(DEPC),  0xffffffff },
00695   { CSR(OPT),   0x00000000 },
00696   { CSR(RCFG),  0x00000000 },
00697   { CSR(CCFG),  0x00000000 },
00698   { CSR(CSR29), 0xffffffff },
00699   { CSR(CSR30), 0xffffffff },
00700   { CSR(CSR31), 0xffffffff },
00701 };
00702 
00703 
00704 /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is
00705    the number of the corresponding pseudoregister.  Otherwise,
00706    mep_raw_to_pseudo[R] == R.  */
00707 static int mep_raw_to_pseudo[MEP_NUM_REGS];
00708 
00709 /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R]
00710    is the number of the underlying raw register.  Otherwise
00711    mep_pseudo_to_raw[R] == R.  */
00712 static int mep_pseudo_to_raw[MEP_NUM_REGS];
00713 
00714 static void
00715 mep_init_pseudoregister_maps (void)
00716 {
00717   int i;
00718 
00719   /* Verify that mep_csr_registers covers all the CSRs, in order.  */
00720   gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR));
00721   gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR));
00722 
00723   /* Verify that the raw and pseudo ranges have matching sizes.  */
00724   gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR));
00725   gdb_assert (NUM_REGS_IN_SET (RAW_CR)  == NUM_REGS_IN_SET (CR32));
00726   gdb_assert (NUM_REGS_IN_SET (RAW_CR)  == NUM_REGS_IN_SET (CR64));
00727   gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR));
00728 
00729   for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
00730     {
00731       struct mep_csr_register *r = &mep_csr_registers[i];
00732 
00733       gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i);
00734       gdb_assert (r->raw    == MEP_FIRST_RAW_CSR_REGNUM + i);
00735     }
00736 
00737   /* Set up the initial  raw<->pseudo mappings.  */
00738   for (i = 0; i < MEP_NUM_REGS; i++)
00739     {
00740       mep_raw_to_pseudo[i] = i;
00741       mep_pseudo_to_raw[i] = i;
00742     }
00743 
00744   /* Add the CSR raw<->pseudo mappings.  */
00745   for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++)
00746     {
00747       struct mep_csr_register *r = &mep_csr_registers[i];
00748 
00749       mep_raw_to_pseudo[r->raw] = r->pseudo;
00750       mep_pseudo_to_raw[r->pseudo] = r->raw;
00751     }
00752 
00753   /* Add the CR raw<->pseudo mappings.  */
00754   for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++)
00755     {
00756       int raw = MEP_FIRST_RAW_CR_REGNUM + i;
00757       int pseudo32 = MEP_FIRST_CR32_REGNUM + i;
00758       int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i;
00759       int pseudo64 = MEP_FIRST_CR64_REGNUM + i;
00760       int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i;
00761 
00762       /* Truly, the raw->pseudo mapping depends on the current module.
00763          But we use the raw->pseudo mapping when we read the debugging
00764          info; at that point, we don't know what module we'll actually
00765          be running yet.  So, we always supply the 64-bit register
00766          numbers; GDB knows how to pick a smaller value out of a
00767          larger register properly.  */
00768       mep_raw_to_pseudo[raw] = pseudo64;
00769       mep_pseudo_to_raw[pseudo32] = raw;
00770       mep_pseudo_to_raw[pseudofp32] = raw;
00771       mep_pseudo_to_raw[pseudo64] = raw;
00772       mep_pseudo_to_raw[pseudofp64] = raw;
00773     }
00774 
00775   /* Add the CCR raw<->pseudo mappings.  */
00776   for (i = 0; i < NUM_REGS_IN_SET (CCR); i++)
00777     {
00778       int raw = MEP_FIRST_RAW_CCR_REGNUM + i;
00779       int pseudo = MEP_FIRST_CCR_REGNUM + i;
00780       mep_raw_to_pseudo[raw] = pseudo;
00781       mep_pseudo_to_raw[pseudo] = raw;
00782     }
00783 }
00784 
00785 
00786 static int
00787 mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg)
00788 {
00789   /* The debug info uses the raw register numbers.  */
00790   return mep_raw_to_pseudo[debug_reg];
00791 }
00792 
00793 
00794 /* Return the size, in bits, of the coprocessor pseudoregister
00795    numbered PSEUDO.  */
00796 static int
00797 mep_pseudo_cr_size (int pseudo)
00798 {
00799   if (IS_CR32_REGNUM (pseudo)
00800       || IS_FP_CR32_REGNUM (pseudo))
00801     return 32;
00802   else if (IS_CR64_REGNUM (pseudo)
00803            || IS_FP_CR64_REGNUM (pseudo))
00804     return 64;
00805   else
00806     gdb_assert_not_reached ("unexpected coprocessor pseudo register");
00807 }
00808 
00809 
00810 /* If the coprocessor pseudoregister numbered PSEUDO is a
00811    floating-point register, return non-zero; if it is an integer
00812    register, return zero.  */
00813 static int
00814 mep_pseudo_cr_is_float (int pseudo)
00815 {
00816   return (IS_FP_CR32_REGNUM (pseudo)
00817           || IS_FP_CR64_REGNUM (pseudo));
00818 }
00819 
00820 
00821 /* Given a coprocessor GPR pseudoregister number, return its index
00822    within that register bank.  */
00823 static int
00824 mep_pseudo_cr_index (int pseudo)
00825 {
00826   if (IS_CR32_REGNUM (pseudo))
00827     return pseudo - MEP_FIRST_CR32_REGNUM;
00828   else if (IS_FP_CR32_REGNUM (pseudo))
00829       return pseudo - MEP_FIRST_FP_CR32_REGNUM;
00830   else if (IS_CR64_REGNUM (pseudo))
00831       return pseudo - MEP_FIRST_CR64_REGNUM;
00832   else if (IS_FP_CR64_REGNUM (pseudo))
00833       return pseudo - MEP_FIRST_FP_CR64_REGNUM;
00834   else
00835     gdb_assert_not_reached ("unexpected coprocessor pseudo register");
00836 }
00837 
00838 
00839 /* Return the me_module index describing the current target.
00840 
00841    If the current target has registers (e.g., simulator, remote
00842    target), then this uses the value of the 'module' register, raw
00843    register MEP_MODULE_REGNUM.  Otherwise, this retrieves the value
00844    from the ELF header's e_flags field of the current executable
00845    file.  */
00846 static CONFIG_ATTR
00847 current_me_module (void)
00848 {
00849   if (target_has_registers)
00850     {
00851       ULONGEST regval;
00852       regcache_cooked_read_unsigned (get_current_regcache (),
00853                                      MEP_MODULE_REGNUM, &regval);
00854       return regval;
00855     }
00856   else
00857     return gdbarch_tdep (target_gdbarch ())->me_module;
00858 }
00859 
00860 
00861 /* Return the set of options for the current target, in the form that
00862    the OPT register would use.
00863 
00864    If the current target has registers (e.g., simulator, remote
00865    target), then this is the actual value of the OPT register.  If the
00866    current target does not have registers (e.g., an executable file),
00867    then use the 'module_opt' field we computed when we build the
00868    gdbarch object for this module.  */
00869 static unsigned int
00870 current_options (void)
00871 {
00872   if (target_has_registers)
00873     {
00874       ULONGEST regval;
00875       regcache_cooked_read_unsigned (get_current_regcache (),
00876                                      MEP_OPT_REGNUM, &regval);
00877       return regval;
00878     }
00879   else
00880     return me_module_opt (current_me_module ());
00881 }
00882 
00883 
00884 /* Return the width of the current me_module's coprocessor data bus,
00885    in bits.  This is either 32 or 64.  */
00886 static int
00887 current_cop_data_bus_width (void)
00888 {
00889   return me_module_cop_data_bus_width (current_me_module ());
00890 }
00891 
00892 
00893 /* Return the keyword table of coprocessor general-purpose register
00894    names appropriate for the me_module we're dealing with.  */
00895 static CGEN_KEYWORD *
00896 current_cr_names (void)
00897 {
00898   const CGEN_HW_ENTRY *hw
00899     = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
00900 
00901   return register_set_keyword_table (hw);
00902 }
00903 
00904 
00905 /* Return non-zero if the coprocessor general-purpose registers are
00906    floating-point values, zero otherwise.  */
00907 static int
00908 current_cr_is_float (void)
00909 {
00910   const CGEN_HW_ENTRY *hw
00911     = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR);
00912 
00913   return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw));
00914 }
00915 
00916 
00917 /* Return the keyword table of coprocessor control register names
00918    appropriate for the me_module we're dealing with.  */
00919 static CGEN_KEYWORD *
00920 current_ccr_names (void)
00921 {
00922   const CGEN_HW_ENTRY *hw
00923     = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR);
00924 
00925   return register_set_keyword_table (hw);
00926 }
00927 
00928 
00929 static const char *
00930 mep_register_name (struct gdbarch *gdbarch, int regnr)
00931 {
00932   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);  
00933 
00934   /* General-purpose registers.  */
00935   static const char *gpr_names[] = {
00936     "r0",   "r1",   "r2",   "r3",   /* 0 */
00937     "r4",   "r5",   "r6",   "r7",   /* 4 */
00938     "fp",   "r9",   "r10",  "r11",  /* 8 */
00939     "r12",  "tp",   "gp",   "sp"    /* 12 */
00940   };
00941 
00942   /* Special-purpose registers.  */
00943   static const char *csr_names[] = {
00944     "pc",   "lp",   "sar",  "",     /* 0  csr3: reserved */ 
00945     "rpb",  "rpe",  "rpc",  "hi",   /* 4 */
00946     "lo",   "",     "",     "",     /* 8  csr9-csr11: reserved */
00947     "mb0",  "me0",  "mb1",  "me1",  /* 12 */
00948 
00949     "psw",  "id",   "tmp",  "epc",  /* 16 */
00950     "exc",  "cfg",  "",     "npc",  /* 20  csr22: reserved */
00951     "dbg",  "depc", "opt",  "rcfg", /* 24 */
00952     "ccfg", "",     "",     ""      /* 28  csr29-csr31: reserved */
00953   };
00954 
00955   if (IS_GPR_REGNUM (regnr))
00956     return gpr_names[regnr - MEP_R0_REGNUM];
00957   else if (IS_CSR_REGNUM (regnr))
00958     {
00959       /* The 'hi' and 'lo' registers are only present on processors
00960          that have the 'MUL' or 'DIV' instructions enabled.  */
00961       if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM)
00962           && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV))))
00963         return "";
00964 
00965       return csr_names[regnr - MEP_FIRST_CSR_REGNUM];
00966     }
00967   else if (IS_CR_REGNUM (regnr))
00968     {
00969       CGEN_KEYWORD *names;
00970       int cr_size;
00971       int cr_is_float;
00972 
00973       /* Does this module have a coprocessor at all?  */
00974       if (! (current_options () & MEP_OPT_COP))
00975         return "";
00976 
00977       names = current_cr_names ();
00978       if (! names)
00979         /* This module's coprocessor has no general-purpose registers.  */
00980         return "";
00981 
00982       cr_size = current_cop_data_bus_width ();
00983       if (cr_size != mep_pseudo_cr_size (regnr))
00984         /* This module's coprocessor's GPR's are of a different size.  */
00985         return "";
00986 
00987       cr_is_float = current_cr_is_float ();
00988       /* The extra ! operators ensure we get boolean equality, not
00989          numeric equality.  */
00990       if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr))
00991         /* This module's coprocessor's GPR's are of a different type.  */
00992         return "";
00993 
00994       return register_name_from_keyword (names, mep_pseudo_cr_index (regnr));
00995     }
00996   else if (IS_CCR_REGNUM (regnr))
00997     {
00998       /* Does this module have a coprocessor at all?  */
00999       if (! (current_options () & MEP_OPT_COP))
01000         return "";
01001 
01002       {
01003         CGEN_KEYWORD *names = current_ccr_names ();
01004 
01005         if (! names)
01006           /* This me_module's coprocessor has no control registers.  */
01007           return "";
01008 
01009         return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM);
01010       }
01011     }
01012 
01013   /* It might be nice to give the 'module' register a name, but that
01014      would affect the output of 'info all-registers', which would
01015      disturb the test suites.  So we leave it invisible.  */
01016   else
01017     return NULL;
01018 }
01019 
01020 
01021 /* Custom register groups for the MeP.  */
01022 static struct reggroup *mep_csr_reggroup; /* control/special */
01023 static struct reggroup *mep_cr_reggroup;  /* coprocessor general-purpose */
01024 static struct reggroup *mep_ccr_reggroup; /* coprocessor control */
01025 
01026 
01027 static int
01028 mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
01029                          struct reggroup *group)
01030 {
01031   /* Filter reserved or unused register numbers.  */
01032   {
01033     const char *name = mep_register_name (gdbarch, regnum);
01034 
01035     if (! name || name[0] == '\0')
01036       return 0;
01037   }
01038 
01039   /* We could separate the GPRs and the CSRs.  Toshiba has approved of
01040      the existing behavior, so we'd want to run that by them.  */
01041   if (group == general_reggroup)
01042     return (IS_GPR_REGNUM (regnum)
01043             || IS_CSR_REGNUM (regnum));
01044 
01045   /* Everything is in the 'all' reggroup, except for the raw CSR's.  */
01046   else if (group == all_reggroup)
01047     return (IS_GPR_REGNUM (regnum)
01048             || IS_CSR_REGNUM (regnum)
01049             || IS_CR_REGNUM (regnum)
01050             || IS_CCR_REGNUM (regnum));
01051 
01052   /* All registers should be saved and restored, except for the raw
01053      CSR's.
01054 
01055      This is probably right if the coprocessor is something like a
01056      floating-point unit, but would be wrong if the coprocessor is
01057      something that does I/O, where register accesses actually cause
01058      externally-visible actions.  But I get the impression that the
01059      coprocessor isn't supposed to do things like that --- you'd use a
01060      hardware engine, perhaps.  */
01061   else if (group == save_reggroup || group == restore_reggroup)
01062     return (IS_GPR_REGNUM (regnum)
01063             || IS_CSR_REGNUM (regnum)
01064             || IS_CR_REGNUM (regnum)
01065             || IS_CCR_REGNUM (regnum));
01066 
01067   else if (group == mep_csr_reggroup)
01068     return IS_CSR_REGNUM (regnum);
01069   else if (group == mep_cr_reggroup)
01070     return IS_CR_REGNUM (regnum);
01071   else if (group == mep_ccr_reggroup)
01072     return IS_CCR_REGNUM (regnum);
01073   else
01074     return 0;
01075 }
01076 
01077 
01078 static struct type *
01079 mep_register_type (struct gdbarch *gdbarch, int reg_nr)
01080 {
01081   /* Coprocessor general-purpose registers may be either 32 or 64 bits
01082      long.  So for them, the raw registers are always 64 bits long (to
01083      keep the 'g' packet format fixed), and the pseudoregisters vary
01084      in length.  */
01085   if (IS_RAW_CR_REGNUM (reg_nr))
01086     return builtin_type (gdbarch)->builtin_uint64;
01087 
01088   /* Since GDB doesn't allow registers to change type, we have two
01089      banks of pseudoregisters for the coprocessor general-purpose
01090      registers: one that gives a 32-bit view, and one that gives a
01091      64-bit view.  We hide or show one or the other depending on the
01092      current module.  */
01093   if (IS_CR_REGNUM (reg_nr))
01094     {
01095       int size = mep_pseudo_cr_size (reg_nr);
01096       if (size == 32)
01097         {
01098           if (mep_pseudo_cr_is_float (reg_nr))
01099             return builtin_type (gdbarch)->builtin_float;
01100           else
01101             return builtin_type (gdbarch)->builtin_uint32;
01102         }
01103       else if (size == 64)
01104         {
01105           if (mep_pseudo_cr_is_float (reg_nr))
01106             return builtin_type (gdbarch)->builtin_double;
01107           else
01108             return builtin_type (gdbarch)->builtin_uint64;
01109         }
01110       else
01111         gdb_assert_not_reached ("unexpected cr size");
01112     }
01113 
01114   /* All other registers are 32 bits long.  */
01115   else
01116     return builtin_type (gdbarch)->builtin_uint32;
01117 }
01118 
01119 
01120 static CORE_ADDR
01121 mep_read_pc (struct regcache *regcache)
01122 {
01123   ULONGEST pc;
01124   regcache_cooked_read_unsigned (regcache, MEP_PC_REGNUM, &pc);
01125   return pc;
01126 }
01127 
01128 static enum register_status
01129 mep_pseudo_cr32_read (struct gdbarch *gdbarch,
01130                       struct regcache *regcache,
01131                       int cookednum,
01132                       void *buf)
01133 {
01134   enum register_status status;
01135   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
01136   /* Read the raw register into a 64-bit buffer, and then return the
01137      appropriate end of that buffer.  */
01138   int rawnum = mep_pseudo_to_raw[cookednum];
01139   gdb_byte buf64[8];
01140 
01141   gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
01142   gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
01143   status = regcache_raw_read (regcache, rawnum, buf64);
01144   if (status == REG_VALID)
01145     {
01146       /* Slow, but legible.  */
01147       store_unsigned_integer (buf, 4, byte_order,
01148                               extract_unsigned_integer (buf64, 8, byte_order));
01149     }
01150   return status;
01151 }
01152 
01153 
01154 static enum register_status
01155 mep_pseudo_cr64_read (struct gdbarch *gdbarch,
01156                       struct regcache *regcache,
01157                       int cookednum,
01158                       void *buf)
01159 {
01160   return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
01161 }
01162 
01163 
01164 static enum register_status
01165 mep_pseudo_register_read (struct gdbarch *gdbarch,
01166                           struct regcache *regcache,
01167                           int cookednum,
01168                           gdb_byte *buf)
01169 {
01170   if (IS_CSR_REGNUM (cookednum)
01171       || IS_CCR_REGNUM (cookednum))
01172     return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf);
01173   else if (IS_CR32_REGNUM (cookednum)
01174            || IS_FP_CR32_REGNUM (cookednum))
01175     return mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf);
01176   else if (IS_CR64_REGNUM (cookednum)
01177            || IS_FP_CR64_REGNUM (cookednum))
01178     return mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf);
01179   else
01180     gdb_assert_not_reached ("unexpected pseudo register");
01181 }
01182 
01183 
01184 static void
01185 mep_pseudo_csr_write (struct gdbarch *gdbarch,
01186                       struct regcache *regcache,
01187                       int cookednum,
01188                       const void *buf)
01189 {
01190   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
01191   int size = register_size (gdbarch, cookednum);
01192   struct mep_csr_register *r
01193     = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM];
01194 
01195   if (r->writeable_bits == 0)
01196     /* A completely read-only register; avoid the read-modify-
01197        write cycle, and juts ignore the entire write.  */
01198     ;
01199   else
01200     {
01201       /* A partially writeable register; do a read-modify-write cycle.  */
01202       ULONGEST old_bits;
01203       ULONGEST new_bits;
01204       ULONGEST mixed_bits;
01205           
01206       regcache_raw_read_unsigned (regcache, r->raw, &old_bits);
01207       new_bits = extract_unsigned_integer (buf, size, byte_order);
01208       mixed_bits = ((r->writeable_bits & new_bits)
01209                     | (~r->writeable_bits & old_bits));
01210       regcache_raw_write_unsigned (regcache, r->raw, mixed_bits);
01211     }
01212 }
01213                       
01214 
01215 static void
01216 mep_pseudo_cr32_write (struct gdbarch *gdbarch,
01217                        struct regcache *regcache,
01218                        int cookednum,
01219                        const void *buf)
01220 {
01221   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
01222   /* Expand the 32-bit value into a 64-bit value, and write that to
01223      the pseudoregister.  */
01224   int rawnum = mep_pseudo_to_raw[cookednum];
01225   gdb_byte buf64[8];
01226   
01227   gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64));
01228   gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4);
01229   /* Slow, but legible.  */
01230   store_unsigned_integer (buf64, 8, byte_order,
01231                           extract_unsigned_integer (buf, 4, byte_order));
01232   regcache_raw_write (regcache, rawnum, buf64);
01233 }
01234 
01235 
01236 static void
01237 mep_pseudo_cr64_write (struct gdbarch *gdbarch,
01238                      struct regcache *regcache,
01239                      int cookednum,
01240                      const void *buf)
01241 {
01242   regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
01243 }
01244 
01245 
01246 static void
01247 mep_pseudo_register_write (struct gdbarch *gdbarch,
01248                            struct regcache *regcache,
01249                            int cookednum,
01250                            const gdb_byte *buf)
01251 {
01252   if (IS_CSR_REGNUM (cookednum))
01253     mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf);
01254   else if (IS_CR32_REGNUM (cookednum)
01255            || IS_FP_CR32_REGNUM (cookednum))
01256     mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf);
01257   else if (IS_CR64_REGNUM (cookednum)
01258            || IS_FP_CR64_REGNUM (cookednum))
01259     mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf);
01260   else if (IS_CCR_REGNUM (cookednum))
01261     regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf);
01262   else
01263     gdb_assert_not_reached ("unexpected pseudo register");
01264 }
01265 
01266 
01267 
01268 /* Disassembly.  */
01269 
01270 /* The mep disassembler needs to know about the section in order to
01271    work correctly.  */
01272 static int
01273 mep_gdb_print_insn (bfd_vma pc, disassemble_info * info)
01274 {
01275   struct obj_section * s = find_pc_section (pc);
01276 
01277   if (s)
01278     {
01279       /* The libopcodes disassembly code uses the section to find the
01280          BFD, the BFD to find the ELF header, the ELF header to find
01281          the me_module index, and the me_module index to select the
01282          right instructions to print.  */
01283       info->section = s->the_bfd_section;
01284       info->arch = bfd_arch_mep;
01285         
01286       return print_insn_mep (pc, info);
01287     }
01288   
01289   return 0;
01290 }
01291 
01292 
01293 /* Prologue analysis.  */
01294 
01295 
01296 /* The MeP has two classes of instructions: "core" instructions, which
01297    are pretty normal RISC chip stuff, and "coprocessor" instructions,
01298    which are mostly concerned with moving data in and out of
01299    coprocessor registers, and branching on coprocessor condition
01300    codes.  There's space in the instruction set for custom coprocessor
01301    instructions, too.
01302 
01303    Instructions can be 16 or 32 bits long; the top two bits of the
01304    first byte indicate the length.  The coprocessor instructions are
01305    mixed in with the core instructions, and there's no easy way to
01306    distinguish them; you have to completely decode them to tell one
01307    from the other.
01308 
01309    The MeP also supports a "VLIW" operation mode, where instructions
01310    always occur in fixed-width bundles.  The bundles are either 32
01311    bits or 64 bits long, depending on a fixed configuration flag.  You
01312    decode the first part of the bundle as normal; if it's a core
01313    instruction, and there's any space left in the bundle, the
01314    remainder of the bundle is a coprocessor instruction, which will
01315    execute in parallel with the core instruction.  If the first part
01316    of the bundle is a coprocessor instruction, it occupies the entire
01317    bundle.
01318 
01319    So, here are all the cases:
01320 
01321    - 32-bit VLIW mode:
01322      Every bundle is four bytes long, and naturally aligned, and can hold
01323      one or two instructions:
01324      - 16-bit core instruction; 16-bit coprocessor instruction
01325        These execute in parallel.
01326      - 32-bit core instruction
01327      - 32-bit coprocessor instruction
01328 
01329    - 64-bit VLIW mode:
01330      Every bundle is eight bytes long, and naturally aligned, and can hold
01331      one or two instructions:
01332      - 16-bit core instruction; 48-bit (!) coprocessor instruction
01333        These execute in parallel.
01334      - 32-bit core instruction; 32-bit coprocessor instruction
01335        These execute in parallel.
01336      - 64-bit coprocessor instruction
01337 
01338    Now, the MeP manual doesn't define any 48- or 64-bit coprocessor
01339    instruction, so I don't really know what's up there; perhaps these
01340    are always the user-defined coprocessor instructions.  */
01341 
01342 
01343 /* Return non-zero if PC is in a VLIW code section, zero
01344    otherwise.  */
01345 static int
01346 mep_pc_in_vliw_section (CORE_ADDR pc)
01347 {
01348   struct obj_section *s = find_pc_section (pc);
01349   if (s)
01350     return (s->the_bfd_section->flags & SEC_MEP_VLIW);
01351   return 0;
01352 }
01353 
01354 
01355 /* Set *INSN to the next core instruction at PC, and return the
01356    address of the next instruction.
01357 
01358    The MeP instruction encoding is endian-dependent.  16- and 32-bit
01359    instructions are encoded as one or two two-byte parts, and each
01360    part is byte-swapped independently.  Thus:
01361 
01362       void
01363       foo (void)
01364       {
01365         asm ("movu $1, 0x123456");
01366         asm ("sb $1,0x5678($2)");
01367         asm ("clip $1, 19");
01368       }
01369 
01370    compiles to this big-endian code:
01371 
01372        0:       d1 56 12 34     movu $1,0x123456
01373        4:       c1 28 56 78     sb $1,22136($2)
01374        8:       f1 01 10 98     clip $1,0x13
01375        c:       70 02           ret
01376 
01377    and this little-endian code:
01378 
01379        0:       56 d1 34 12     movu $1,0x123456
01380        4:       28 c1 78 56     sb $1,22136($2)
01381        8:       01 f1 98 10     clip $1,0x13
01382        c:       02 70           ret
01383 
01384    Instructions are returned in *INSN in an endian-independent form: a
01385    given instruction always appears in *INSN the same way, regardless
01386    of whether the instruction stream is big-endian or little-endian.
01387 
01388    *INSN's most significant 16 bits are the first (i.e., at lower
01389    addresses) 16 bit part of the instruction.  Its least significant
01390    16 bits are the second (i.e., higher-addressed) 16 bit part of the
01391    instruction, or zero for a 16-bit instruction.  Both 16-bit parts
01392    are fetched using the current endianness.
01393 
01394    So, the *INSN values for the instruction sequence above would be
01395    the following, in either endianness:
01396 
01397        0xd1561234       movu $1,0x123456     
01398        0xc1285678       sb $1,22136($2)
01399        0xf1011098       clip $1,0x13
01400        0x70020000       ret
01401 
01402    (In a sense, it would be more natural to return 16-bit instructions
01403    in the least significant 16 bits of *INSN, but that would be
01404    ambiguous.  In order to tell whether you're looking at a 16- or a
01405    32-bit instruction, you have to consult the major opcode field ---
01406    the most significant four bits of the instruction's first 16-bit
01407    part.  But if we put 16-bit instructions at the least significant
01408    end of *INSN, then you don't know where to find the major opcode
01409    field until you know if it's a 16- or a 32-bit instruction ---
01410    which is where we started.)
01411 
01412    If PC points to a core / coprocessor bundle in a VLIW section, set
01413    *INSN to the core instruction, and return the address of the next
01414    bundle.  This has the effect of skipping the bundled coprocessor
01415    instruction.  That's okay, since coprocessor instructions aren't
01416    significant to prologue analysis --- for the time being,
01417    anyway.  */
01418 
01419 static CORE_ADDR 
01420 mep_get_insn (struct gdbarch *gdbarch, CORE_ADDR pc, unsigned long *insn)
01421 {
01422   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
01423   int pc_in_vliw_section;
01424   int vliw_mode;
01425   int insn_len;
01426   gdb_byte buf[2];
01427 
01428   *insn = 0;
01429 
01430   /* Are we in a VLIW section?  */
01431   pc_in_vliw_section = mep_pc_in_vliw_section (pc);
01432   if (pc_in_vliw_section)
01433     {
01434       /* Yes, find out which bundle size.  */
01435       vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64);
01436 
01437       /* If PC is in a VLIW section, but the current core doesn't say
01438          that it supports either VLIW mode, then we don't have enough
01439          information to parse the instruction stream it contains.
01440          Since the "undifferentiated" standard core doesn't have
01441          either VLIW mode bit set, this could happen.
01442 
01443          But it shouldn't be an error to (say) set a breakpoint in a
01444          VLIW section, if you know you'll never reach it.  (Perhaps
01445          you have a script that sets a bunch of standard breakpoints.)
01446 
01447          So we'll just return zero here, and hope for the best.  */
01448       if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64)))
01449         return 0;
01450 
01451       /* If both VL32 and VL64 are set, that's bogus, too.  */
01452       if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64))
01453         return 0;
01454     }
01455   else
01456     vliw_mode = 0;
01457 
01458   read_memory (pc, buf, sizeof (buf));
01459   *insn = extract_unsigned_integer (buf, 2, byte_order) << 16;
01460 
01461   /* The major opcode --- the top four bits of the first 16-bit
01462      part --- indicates whether this instruction is 16 or 32 bits
01463      long.  All 32-bit instructions have a major opcode whose top
01464      two bits are 11; all the rest are 16-bit instructions.  */
01465   if ((*insn & 0xc0000000) == 0xc0000000)
01466     {
01467       /* Fetch the second 16-bit part of the instruction.  */
01468       read_memory (pc + 2, buf, sizeof (buf));
01469       *insn = *insn | extract_unsigned_integer (buf, 2, byte_order);
01470     }
01471 
01472   /* If we're in VLIW code, then the VLIW width determines the address
01473      of the next instruction.  */
01474   if (vliw_mode)
01475     {
01476       /* In 32-bit VLIW code, all bundles are 32 bits long.  We ignore the
01477          coprocessor half of a core / copro bundle.  */
01478       if (vliw_mode == MEP_OPT_VL32)
01479         insn_len = 4;
01480 
01481       /* In 64-bit VLIW code, all bundles are 64 bits long.  We ignore the
01482          coprocessor half of a core / copro bundle.  */
01483       else if (vliw_mode == MEP_OPT_VL64)
01484         insn_len = 8;
01485 
01486       /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode.  */
01487       else
01488         gdb_assert_not_reached ("unexpected vliw mode");
01489     }
01490   
01491   /* Otherwise, the top two bits of the major opcode are (again) what
01492      we need to check.  */
01493   else if ((*insn & 0xc0000000) == 0xc0000000)
01494     insn_len = 4;
01495   else
01496     insn_len = 2;
01497 
01498   return pc + insn_len;
01499 }
01500 
01501 
01502 /* Sign-extend the LEN-bit value N.  */
01503 #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1)))
01504 
01505 /* Return the LEN-bit field at POS from I.  */
01506 #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1))
01507 
01508 /* Like FIELD, but sign-extend the field's value.  */
01509 #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len)))
01510 
01511 
01512 /* Macros for decoding instructions.
01513 
01514    Remember that 16-bit instructions are placed in bits 16..31 of i,
01515    not at the least significant end; this means that the major opcode
01516    field is always in the same place, regardless of the width of the
01517    instruction.  As a reminder of this, we show the lower 16 bits of a
01518    16-bit instruction as xxxx_xxxx_xxxx_xxxx.  */
01519 
01520 /* SB Rn,(Rm)                 0000_nnnn_mmmm_1000 */
01521 /* SH Rn,(Rm)                 0000_nnnn_mmmm_1001 */
01522 /* SW Rn,(Rm)                 0000_nnnn_mmmm_1010 */
01523 
01524 /* SW Rn,disp16(Rm)           1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */
01525 #define IS_SW(i)              (((i) & 0xf00f0000) == 0xc00a0000)
01526 /* SB Rn,disp16(Rm)           1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */
01527 #define IS_SB(i)              (((i) & 0xf00f0000) == 0xc0080000)
01528 /* SH Rn,disp16(Rm)           1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */
01529 #define IS_SH(i)              (((i) & 0xf00f0000) == 0xc0090000)
01530 #define SWBH_32_BASE(i)       (FIELD (i, 20, 4))
01531 #define SWBH_32_SOURCE(i)     (FIELD (i, 24, 4))
01532 #define SWBH_32_OFFSET(i)     (SFIELD (i, 0, 16))
01533 
01534 /* SW Rn,disp7.align4(SP)     0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */
01535 #define IS_SW_IMMD(i)         (((i) & 0xf0830000) == 0x40020000)
01536 #define SW_IMMD_SOURCE(i)     (FIELD (i, 24, 4))
01537 #define SW_IMMD_OFFSET(i)     (FIELD (i, 18, 5) << 2)
01538 
01539 /* SW Rn,(Rm)                 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */
01540 #define IS_SW_REG(i)          (((i) & 0xf00f0000) == 0x000a0000)
01541 #define SW_REG_SOURCE(i)      (FIELD (i, 24, 4))
01542 #define SW_REG_BASE(i)        (FIELD (i, 20, 4))
01543 
01544 /* ADD3 Rl,Rn,Rm              1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */
01545 #define IS_ADD3_16_REG(i)     (((i) & 0xf0000000) == 0x90000000)
01546 #define ADD3_16_REG_SRC1(i)   (FIELD (i, 20, 4))               /* n */
01547 #define ADD3_16_REG_SRC2(i)   (FIELD (i, 24, 4))               /* m */
01548 
01549 /* ADD3 Rn,Rm,imm16           1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */
01550 #define IS_ADD3_32(i)         (((i) & 0xf00f0000) == 0xc0000000)
01551 #define ADD3_32_TARGET(i)     (FIELD (i, 24, 4))
01552 #define ADD3_32_SOURCE(i)     (FIELD (i, 20, 4))
01553 #define ADD3_32_OFFSET(i)     (SFIELD (i, 0, 16))
01554 
01555 /* ADD3 Rn,SP,imm7.align4     0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */
01556 #define IS_ADD3_16(i)         (((i) & 0xf0830000) == 0x40000000)
01557 #define ADD3_16_TARGET(i)     (FIELD (i, 24, 4))
01558 #define ADD3_16_OFFSET(i)     (FIELD (i, 18, 5) << 2)
01559 
01560 /* ADD Rn,imm6                0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */
01561 #define IS_ADD(i)             (((i) & 0xf0030000) == 0x60000000)
01562 #define ADD_TARGET(i)         (FIELD (i, 24, 4))
01563 #define ADD_OFFSET(i)         (SFIELD (i, 18, 6))
01564 
01565 /* LDC Rn,imm5                0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx
01566                               imm5 = I||i[7:4] */
01567 #define IS_LDC(i)             (((i) & 0xf00e0000) == 0x700a0000)
01568 #define LDC_IMM(i)            ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4))
01569 #define LDC_TARGET(i)         (FIELD (i, 24, 4))
01570 
01571 /* LW Rn,disp16(Rm)           1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd  */
01572 #define IS_LW(i)              (((i) & 0xf00f0000) == 0xc00e0000)
01573 #define LW_TARGET(i)          (FIELD (i, 24, 4))
01574 #define LW_BASE(i)            (FIELD (i, 20, 4))
01575 #define LW_OFFSET(i)          (SFIELD (i, 0, 16))
01576 
01577 /* MOV Rn,Rm                  0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */
01578 #define IS_MOV(i)             (((i) & 0xf00f0000) == 0x00000000)
01579 #define MOV_TARGET(i)         (FIELD (i, 24, 4))
01580 #define MOV_SOURCE(i)         (FIELD (i, 20, 4))
01581 
01582 /* BRA disp12.align2          1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */
01583 #define IS_BRA(i)             (((i) & 0xf0010000) == 0xb0000000)
01584 #define BRA_DISP(i)           (SFIELD (i, 17, 11) << 1)
01585 
01586 
01587 /* This structure holds the results of a prologue analysis.  */
01588 struct mep_prologue
01589 {
01590   /* The architecture for which we generated this prologue info.  */
01591   struct gdbarch *gdbarch;
01592 
01593   /* The offset from the frame base to the stack pointer --- always
01594      zero or negative.
01595 
01596      Calling this a "size" is a bit misleading, but given that the
01597      stack grows downwards, using offsets for everything keeps one
01598      from going completely sign-crazy: you never change anything's
01599      sign for an ADD instruction; always change the second operand's
01600      sign for a SUB instruction; and everything takes care of
01601      itself.  */
01602   int frame_size;
01603 
01604   /* Non-zero if this function has initialized the frame pointer from
01605      the stack pointer, zero otherwise.  */
01606   int has_frame_ptr;
01607 
01608   /* If has_frame_ptr is non-zero, this is the offset from the frame
01609      base to where the frame pointer points.  This is always zero or
01610      negative.  */
01611   int frame_ptr_offset;
01612 
01613   /* The address of the first instruction at which the frame has been
01614      set up and the arguments are where the debug info says they are
01615      --- as best as we can tell.  */
01616   CORE_ADDR prologue_end;
01617 
01618   /* reg_offset[R] is the offset from the CFA at which register R is
01619      saved, or 1 if register R has not been saved.  (Real values are
01620      always zero or negative.)  */
01621   int reg_offset[MEP_NUM_REGS];
01622 };
01623 
01624 /* Return non-zero if VALUE is an incoming argument register.  */
01625 
01626 static int
01627 is_arg_reg (pv_t value)
01628 {
01629   return (value.kind == pvk_register
01630           && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM
01631           && value.k == 0);
01632 }
01633 
01634 /* Return non-zero if a store of REG's current value VALUE to ADDR is
01635    probably spilling an argument register to its stack slot in STACK.
01636    Such instructions should be included in the prologue, if possible.
01637 
01638    The store is a spill if:
01639    - the value being stored is REG's original value;
01640    - the value has not already been stored somewhere in STACK; and
01641    - ADDR is a stack slot's address (e.g., relative to the original
01642      value of the SP).  */
01643 static int
01644 is_arg_spill (struct gdbarch *gdbarch, pv_t value, pv_t addr,
01645               struct pv_area *stack)
01646 {
01647   return (is_arg_reg (value)
01648           && pv_is_register (addr, MEP_SP_REGNUM)
01649           && ! pv_area_find_reg (stack, gdbarch, value.reg, 0));
01650 }
01651 
01652 
01653 /* Function for finding saved registers in a 'struct pv_area'; we pass
01654    this to pv_area_scan.
01655 
01656    If VALUE is a saved register, ADDR says it was saved at a constant
01657    offset from the frame base, and SIZE indicates that the whole
01658    register was saved, record its offset in RESULT_UNTYPED.  */
01659 static void
01660 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
01661 {
01662   struct mep_prologue *result = (struct mep_prologue *) result_untyped;
01663 
01664   if (value.kind == pvk_register
01665       && value.k == 0
01666       && pv_is_register (addr, MEP_SP_REGNUM)
01667       && size == register_size (result->gdbarch, value.reg))
01668     result->reg_offset[value.reg] = addr.k;
01669 }
01670 
01671 
01672 /* Analyze a prologue starting at START_PC, going no further than
01673    LIMIT_PC.  Fill in RESULT as appropriate.  */
01674 static void
01675 mep_analyze_prologue (struct gdbarch *gdbarch,
01676                       CORE_ADDR start_pc, CORE_ADDR limit_pc,
01677                       struct mep_prologue *result)
01678 {
01679   CORE_ADDR pc;
01680   unsigned long insn;
01681   int rn;
01682   int found_lp = 0;
01683   pv_t reg[MEP_NUM_REGS];
01684   struct pv_area *stack;
01685   struct cleanup *back_to;
01686   CORE_ADDR after_last_frame_setup_insn = start_pc;
01687 
01688   memset (result, 0, sizeof (*result));
01689   result->gdbarch = gdbarch;
01690 
01691   for (rn = 0; rn < MEP_NUM_REGS; rn++)
01692     {
01693       reg[rn] = pv_register (rn, 0);
01694       result->reg_offset[rn] = 1;
01695     }
01696 
01697   stack = make_pv_area (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch));
01698   back_to = make_cleanup_free_pv_area (stack);
01699 
01700   pc = start_pc;
01701   while (pc < limit_pc)
01702     {
01703       CORE_ADDR next_pc;
01704       pv_t pre_insn_fp, pre_insn_sp;
01705 
01706       next_pc = mep_get_insn (gdbarch, pc, &insn);
01707 
01708       /* A zero return from mep_get_insn means that either we weren't
01709          able to read the instruction from memory, or that we don't
01710          have enough information to be able to reliably decode it.  So
01711          we'll store here and hope for the best.  */
01712       if (! next_pc)
01713         break;
01714 
01715       /* Note the current values of the SP and FP, so we can tell if
01716          this instruction changed them, below.  */
01717       pre_insn_fp = reg[MEP_FP_REGNUM];
01718       pre_insn_sp = reg[MEP_SP_REGNUM];
01719 
01720       if (IS_ADD (insn))
01721         {
01722           int rn = ADD_TARGET (insn);
01723           CORE_ADDR imm6 = ADD_OFFSET (insn);
01724 
01725           reg[rn] = pv_add_constant (reg[rn], imm6);
01726         }
01727       else if (IS_ADD3_16 (insn))
01728         {
01729           int rn = ADD3_16_TARGET (insn);
01730           int imm7 = ADD3_16_OFFSET (insn);
01731 
01732           reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7);
01733         }
01734       else if (IS_ADD3_32 (insn))
01735         {
01736           int rn = ADD3_32_TARGET (insn);
01737           int rm = ADD3_32_SOURCE (insn);
01738           int imm16 = ADD3_32_OFFSET (insn);
01739 
01740           reg[rn] = pv_add_constant (reg[rm], imm16);
01741         }
01742       else if (IS_SW_REG (insn))
01743         {
01744           int rn = SW_REG_SOURCE (insn);
01745           int rm = SW_REG_BASE (insn);
01746 
01747           /* If simulating this store would require us to forget
01748              everything we know about the stack frame in the name of
01749              accuracy, it would be better to just quit now.  */
01750           if (pv_area_store_would_trash (stack, reg[rm]))
01751             break;
01752           
01753           if (is_arg_spill (gdbarch, reg[rn], reg[rm], stack))
01754             after_last_frame_setup_insn = next_pc;
01755 
01756           pv_area_store (stack, reg[rm], 4, reg[rn]);
01757         }
01758       else if (IS_SW_IMMD (insn))
01759         {
01760           int rn = SW_IMMD_SOURCE (insn);
01761           int offset = SW_IMMD_OFFSET (insn);
01762           pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset);
01763 
01764           /* If simulating this store would require us to forget
01765              everything we know about the stack frame in the name of
01766              accuracy, it would be better to just quit now.  */
01767           if (pv_area_store_would_trash (stack, addr))
01768             break;
01769 
01770           if (is_arg_spill (gdbarch, reg[rn], addr, stack))
01771             after_last_frame_setup_insn = next_pc;
01772 
01773           pv_area_store (stack, addr, 4, reg[rn]);
01774         }
01775       else if (IS_MOV (insn))
01776         {
01777           int rn = MOV_TARGET (insn);
01778           int rm = MOV_SOURCE (insn);
01779 
01780           reg[rn] = reg[rm];
01781 
01782           if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm]))
01783             after_last_frame_setup_insn = next_pc;
01784         }
01785       else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn))
01786         {
01787           int rn = SWBH_32_SOURCE (insn);
01788           int rm = SWBH_32_BASE (insn);
01789           int disp = SWBH_32_OFFSET (insn);
01790           int size = (IS_SB (insn) ? 1
01791                       : IS_SH (insn) ? 2
01792                       : (gdb_assert (IS_SW (insn)), 4));
01793           pv_t addr = pv_add_constant (reg[rm], disp);
01794 
01795           if (pv_area_store_would_trash (stack, addr))
01796             break;
01797 
01798           if (is_arg_spill (gdbarch, reg[rn], addr, stack))
01799             after_last_frame_setup_insn = next_pc;
01800 
01801           pv_area_store (stack, addr, size, reg[rn]);
01802         }
01803       else if (IS_LDC (insn))
01804         {
01805           int rn = LDC_TARGET (insn);
01806           int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM;
01807 
01808           reg[rn] = reg[cr];
01809         }
01810       else if (IS_LW (insn))
01811         {
01812           int rn = LW_TARGET (insn);
01813           int rm = LW_BASE (insn);
01814           int offset = LW_OFFSET (insn);
01815           pv_t addr = pv_add_constant (reg[rm], offset);
01816 
01817           reg[rn] = pv_area_fetch (stack, addr, 4);
01818         }
01819       else if (IS_BRA (insn) && BRA_DISP (insn) > 0)
01820         {
01821           /* When a loop appears as the first statement of a function
01822              body, gcc 4.x will use a BRA instruction to branch to the
01823              loop condition checking code.  This BRA instruction is
01824              marked as part of the prologue.  We therefore set next_pc
01825              to this branch target and also stop the prologue scan.
01826              The instructions at and beyond the branch target should
01827              no longer be associated with the prologue.
01828              
01829              Note that we only consider forward branches here.  We
01830              presume that a forward branch is being used to skip over
01831              a loop body.
01832              
01833              A backwards branch is covered by the default case below.
01834              If we were to encounter a backwards branch, that would
01835              most likely mean that we've scanned through a loop body.
01836              We definitely want to stop the prologue scan when this
01837              happens and that is precisely what is done by the default
01838              case below.  */
01839           next_pc = pc + BRA_DISP (insn);
01840           after_last_frame_setup_insn = next_pc;
01841           break;
01842         }
01843       else
01844         /* We've hit some instruction we don't know how to simulate.
01845            Strictly speaking, we should set every value we're
01846            tracking to "unknown".  But we'll be optimistic, assume
01847            that we have enough information already, and stop
01848            analysis here.  */
01849         break;
01850 
01851       /* If this instruction changed the FP or decreased the SP (i.e.,
01852          allocated more stack space), then this may be a good place to
01853          declare the prologue finished.  However, there are some
01854          exceptions:
01855 
01856          - If the instruction just changed the FP back to its original
01857            value, then that's probably a restore instruction.  The
01858            prologue should definitely end before that.  
01859 
01860          - If the instruction increased the value of the SP (that is,
01861            shrunk the frame), then it's probably part of a frame
01862            teardown sequence, and the prologue should end before that.  */
01863 
01864       if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp))
01865         {
01866           if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0))
01867             after_last_frame_setup_insn = next_pc;
01868         }
01869       else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp))
01870         {
01871           /* The comparison of constants looks odd, there, because .k
01872              is unsigned.  All it really means is that the new value
01873              is lower than it was before the instruction.  */
01874           if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM)
01875               && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)
01876               && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k)
01877                   < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k)))
01878             after_last_frame_setup_insn = next_pc;
01879         }
01880 
01881       pc = next_pc;
01882     }
01883 
01884   /* Is the frame size (offset, really) a known constant?  */
01885   if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM))
01886     result->frame_size = reg[MEP_SP_REGNUM].k;
01887 
01888   /* Was the frame pointer initialized?  */
01889   if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM))
01890     {
01891       result->has_frame_ptr = 1;
01892       result->frame_ptr_offset = reg[MEP_FP_REGNUM].k;
01893     }
01894 
01895   /* Record where all the registers were saved.  */
01896   pv_area_scan (stack, check_for_saved, (void *) result);
01897 
01898   result->prologue_end = after_last_frame_setup_insn;
01899 
01900   do_cleanups (back_to);
01901 }
01902 
01903 
01904 static CORE_ADDR
01905 mep_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
01906 {
01907   const char *name;
01908   CORE_ADDR func_addr, func_end;
01909   struct mep_prologue p;
01910 
01911   /* Try to find the extent of the function that contains PC.  */
01912   if (! find_pc_partial_function (pc, &name, &func_addr, &func_end))
01913     return pc;
01914 
01915   mep_analyze_prologue (gdbarch, pc, func_end, &p);
01916   return p.prologue_end;
01917 }
01918 
01919 
01920 
01921 /* Breakpoints.  */
01922 
01923 static const unsigned char *
01924 mep_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
01925 {
01926   static unsigned char breakpoint[] = { 0x70, 0x32 };
01927   *lenptr = sizeof (breakpoint);
01928   return breakpoint;
01929 }
01930 
01931 
01932 
01933 /* Frames and frame unwinding.  */
01934 
01935 
01936 static struct mep_prologue *
01937 mep_analyze_frame_prologue (struct frame_info *this_frame,
01938                             void **this_prologue_cache)
01939 {
01940   if (! *this_prologue_cache)
01941     {
01942       CORE_ADDR func_start, stop_addr;
01943 
01944       *this_prologue_cache 
01945         = FRAME_OBSTACK_ZALLOC (struct mep_prologue);
01946 
01947       func_start = get_frame_func (this_frame);
01948       stop_addr = get_frame_pc (this_frame);
01949 
01950       /* If we couldn't find any function containing the PC, then
01951          just initialize the prologue cache, but don't do anything.  */
01952       if (! func_start)
01953         stop_addr = func_start;
01954 
01955       mep_analyze_prologue (get_frame_arch (this_frame),
01956                             func_start, stop_addr, *this_prologue_cache);
01957     }
01958 
01959   return *this_prologue_cache;
01960 }
01961 
01962 
01963 /* Given the next frame and a prologue cache, return this frame's
01964    base.  */
01965 static CORE_ADDR
01966 mep_frame_base (struct frame_info *this_frame,
01967                 void **this_prologue_cache)
01968 {
01969   struct mep_prologue *p
01970     = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
01971 
01972   /* In functions that use alloca, the distance between the stack
01973      pointer and the frame base varies dynamically, so we can't use
01974      the SP plus static information like prologue analysis to find the
01975      frame base.  However, such functions must have a frame pointer,
01976      to be able to restore the SP on exit.  So whenever we do have a
01977      frame pointer, use that to find the base.  */
01978   if (p->has_frame_ptr)
01979     {
01980       CORE_ADDR fp
01981         = get_frame_register_unsigned (this_frame, MEP_FP_REGNUM);
01982       return fp - p->frame_ptr_offset;
01983     }
01984   else
01985     {
01986       CORE_ADDR sp
01987         = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM);
01988       return sp - p->frame_size;
01989     }
01990 }
01991 
01992 
01993 static void
01994 mep_frame_this_id (struct frame_info *this_frame,
01995                    void **this_prologue_cache,
01996                    struct frame_id *this_id)
01997 {
01998   *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache),
01999                              get_frame_func (this_frame));
02000 }
02001 
02002 
02003 static struct value *
02004 mep_frame_prev_register (struct frame_info *this_frame,
02005                          void **this_prologue_cache, int regnum)
02006 {
02007   struct mep_prologue *p
02008     = mep_analyze_frame_prologue (this_frame, this_prologue_cache);
02009 
02010   /* There are a number of complications in unwinding registers on the
02011      MeP, having to do with core functions calling VLIW functions and
02012      vice versa.
02013 
02014      The least significant bit of the link register, LP.LTOM, is the
02015      VLIW mode toggle bit: it's set if a core function called a VLIW
02016      function, or vice versa, and clear when the caller and callee
02017      were both in the same mode.
02018 
02019      So, if we're asked to unwind the PC, then we really want to
02020      unwind the LP and clear the least significant bit.  (Real return
02021      addresses are always even.)  And if we want to unwind the program
02022      status word (PSW), we need to toggle PSW.OM if LP.LTOM is set.
02023 
02024      Tweaking the register values we return in this way means that the
02025      bits in BUFFERP[] are not the same as the bits you'd find at
02026      ADDRP in the inferior, so we make sure lvalp is not_lval when we
02027      do this.  */
02028   if (regnum == MEP_PC_REGNUM)
02029     {
02030       struct value *value;
02031       CORE_ADDR lp;
02032       value = mep_frame_prev_register (this_frame, this_prologue_cache,
02033                                        MEP_LP_REGNUM);
02034       lp = value_as_long (value);
02035       release_value (value);
02036       value_free (value);
02037 
02038       return frame_unwind_got_constant (this_frame, regnum, lp & ~1);
02039     }
02040   else
02041     {
02042       CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache);
02043       struct value *value;
02044 
02045       /* Our caller's SP is our frame base.  */
02046       if (regnum == MEP_SP_REGNUM)
02047         return frame_unwind_got_constant (this_frame, regnum, frame_base);
02048 
02049       /* If prologue analysis says we saved this register somewhere,
02050          return a description of the stack slot holding it.  */
02051       if (p->reg_offset[regnum] != 1)
02052         value = frame_unwind_got_memory (this_frame, regnum,
02053                                          frame_base + p->reg_offset[regnum]);
02054 
02055       /* Otherwise, presume we haven't changed the value of this
02056          register, and get it from the next frame.  */
02057       else
02058         value = frame_unwind_got_register (this_frame, regnum, regnum);
02059 
02060       /* If we need to toggle the operating mode, do so.  */
02061       if (regnum == MEP_PSW_REGNUM)
02062         {
02063           CORE_ADDR psw, lp;
02064 
02065           psw = value_as_long (value);
02066           release_value (value);
02067           value_free (value);
02068 
02069           /* Get the LP's value, too.  */
02070           value = get_frame_register_value (this_frame, MEP_LP_REGNUM);
02071           lp = value_as_long (value);
02072           release_value (value);
02073           value_free (value);
02074 
02075           /* If LP.LTOM is set, then toggle PSW.OM.  */
02076           if (lp & 0x1)
02077             psw ^= 0x1000;
02078 
02079           return frame_unwind_got_constant (this_frame, regnum, psw);
02080         }
02081 
02082       return value;
02083     }
02084 }
02085 
02086 
02087 static const struct frame_unwind mep_frame_unwind = {
02088   NORMAL_FRAME,
02089   default_frame_unwind_stop_reason,
02090   mep_frame_this_id,
02091   mep_frame_prev_register,
02092   NULL,
02093   default_frame_sniffer
02094 };
02095 
02096 
02097 /* Our general unwinding function can handle unwinding the PC.  */
02098 static CORE_ADDR
02099 mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
02100 {
02101   return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM);
02102 }
02103 
02104 
02105 /* Our general unwinding function can handle unwinding the SP.  */
02106 static CORE_ADDR
02107 mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
02108 {
02109   return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM);
02110 }
02111 
02112 
02113 
02114 /* Return values.  */
02115 
02116 
02117 static int
02118 mep_use_struct_convention (struct type *type)
02119 {
02120   return (TYPE_LENGTH (type) > MEP_GPR_SIZE);
02121 }
02122 
02123 
02124 static void
02125 mep_extract_return_value (struct gdbarch *arch,
02126                           struct type *type,
02127                           struct regcache *regcache,
02128                           gdb_byte *valbuf)
02129 {
02130   int byte_order = gdbarch_byte_order (arch);
02131 
02132   /* Values that don't occupy a full register appear at the less
02133      significant end of the value.  This is the offset to where the
02134      value starts.  */
02135   int offset;
02136 
02137   /* Return values > MEP_GPR_SIZE bytes are returned in memory,
02138      pointed to by R0.  */
02139   gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE);
02140 
02141   if (byte_order == BFD_ENDIAN_BIG)
02142     offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
02143   else
02144     offset = 0;
02145 
02146   /* Return values that do fit in a single register are returned in R0.  */
02147   regcache_cooked_read_part (regcache, MEP_R0_REGNUM,
02148                              offset, TYPE_LENGTH (type),
02149                              valbuf);
02150 }
02151 
02152 
02153 static void
02154 mep_store_return_value (struct gdbarch *arch,
02155                         struct type *type,
02156                         struct regcache *regcache,
02157                         const gdb_byte *valbuf)
02158 {
02159   int byte_order = gdbarch_byte_order (arch);
02160 
02161   /* Values that fit in a single register go in R0.  */
02162   if (TYPE_LENGTH (type) <= MEP_GPR_SIZE)
02163     {
02164       /* Values that don't occupy a full register appear at the least
02165          significant end of the value.  This is the offset to where the
02166          value starts.  */
02167       int offset;
02168 
02169       if (byte_order == BFD_ENDIAN_BIG)
02170         offset = MEP_GPR_SIZE - TYPE_LENGTH (type);
02171       else
02172         offset = 0;
02173 
02174       regcache_cooked_write_part (regcache, MEP_R0_REGNUM,
02175                                   offset, TYPE_LENGTH (type),
02176                                   valbuf);
02177     }
02178 
02179   /* Return values larger than a single register are returned in
02180      memory, pointed to by R0.  Unfortunately, we can't count on R0
02181      pointing to the return buffer, so we raise an error here.  */
02182   else
02183     error (_("\
02184 GDB cannot set return values larger than four bytes; the Media Processor's\n\
02185 calling conventions do not provide enough information to do this.\n\
02186 Try using the 'return' command with no argument."));
02187 }
02188 
02189 static enum return_value_convention
02190 mep_return_value (struct gdbarch *gdbarch, struct value *function,
02191                   struct type *type, struct regcache *regcache,
02192                   gdb_byte *readbuf, const gdb_byte *writebuf)
02193 {
02194   if (mep_use_struct_convention (type))
02195     {
02196       if (readbuf)
02197         {
02198           ULONGEST addr;
02199           /* Although the address of the struct buffer gets passed in R1, it's
02200              returned in R0.  Fetch R0's value and then read the memory
02201              at that address.  */
02202           regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr);
02203           read_memory (addr, readbuf, TYPE_LENGTH (type));
02204         }
02205       if (writebuf)
02206         {
02207           /* Return values larger than a single register are returned in
02208              memory, pointed to by R0.  Unfortunately, we can't count on R0
02209              pointing to the return buffer, so we raise an error here.  */
02210           error (_("\
02211 GDB cannot set return values larger than four bytes; the Media Processor's\n\
02212 calling conventions do not provide enough information to do this.\n\
02213 Try using the 'return' command with no argument."));
02214         }
02215       return RETURN_VALUE_ABI_RETURNS_ADDRESS;
02216     }
02217 
02218   if (readbuf)
02219     mep_extract_return_value (gdbarch, type, regcache, readbuf);
02220   if (writebuf)
02221     mep_store_return_value (gdbarch, type, regcache, writebuf);
02222 
02223   return RETURN_VALUE_REGISTER_CONVENTION;
02224 }
02225 
02226 
02227 /* Inferior calls.  */
02228 
02229 
02230 static CORE_ADDR
02231 mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
02232 {
02233   /* Require word alignment.  */
02234   return sp & -4;
02235 }
02236 
02237 
02238 /* From "lang_spec2.txt":
02239 
02240    4.2 Calling conventions
02241 
02242    4.2.1 Core register conventions
02243 
02244    - Parameters should be evaluated from left to right, and they
02245      should be held in $1,$2,$3,$4 in order.  The fifth parameter or
02246      after should be held in the stack.  If the size is larger than 4
02247      bytes in the first four parameters, the pointer should be held in
02248      the registers instead.  If the size is larger than 4 bytes in the
02249      fifth parameter or after, the pointer should be held in the stack.
02250 
02251    - Return value of a function should be held in register $0.  If the
02252      size of return value is larger than 4 bytes, $1 should hold the
02253      pointer pointing memory that would hold the return value.  In this
02254      case, the first parameter should be held in $2, the second one in
02255      $3, and the third one in $4, and the forth parameter or after
02256      should be held in the stack.
02257 
02258    [This doesn't say so, but arguments shorter than four bytes are
02259    passed in the least significant end of a four-byte word when
02260    they're passed on the stack.]  */
02261 
02262 
02263 /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too
02264    large to fit in a register, save it on the stack, and place its
02265    address in COPY[i].  SP is the initial stack pointer; return the
02266    new stack pointer.  */
02267 static CORE_ADDR
02268 push_large_arguments (CORE_ADDR sp, int argc, struct value **argv,
02269                       CORE_ADDR copy[])
02270 {
02271   int i;
02272 
02273   for (i = 0; i < argc; i++)
02274     {
02275       unsigned arg_len = TYPE_LENGTH (value_type (argv[i]));
02276 
02277       if (arg_len > MEP_GPR_SIZE)
02278         {
02279           /* Reserve space for the copy, and then round the SP down, to
02280              make sure it's all aligned properly.  */
02281           sp = (sp - arg_len) & -4;
02282           write_memory (sp, value_contents (argv[i]), arg_len);
02283           copy[i] = sp;
02284         }
02285     }
02286 
02287   return sp;
02288 }
02289 
02290 
02291 static CORE_ADDR
02292 mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
02293                      struct regcache *regcache, CORE_ADDR bp_addr,
02294                      int argc, struct value **argv, CORE_ADDR sp,
02295                      int struct_return,
02296                      CORE_ADDR struct_addr)
02297 {
02298   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
02299   CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0]));
02300   CORE_ADDR func_addr = find_function_addr (function, NULL);
02301   int i;
02302 
02303   /* The number of the next register available to hold an argument.  */
02304   int arg_reg;
02305 
02306   /* The address of the next stack slot available to hold an argument.  */
02307   CORE_ADDR arg_stack;
02308 
02309   /* The address of the end of the stack area for arguments.  This is
02310      just for error checking.  */
02311   CORE_ADDR arg_stack_end;
02312   
02313   sp = push_large_arguments (sp, argc, argv, copy);
02314 
02315   /* Reserve space for the stack arguments, if any.  */
02316   arg_stack_end = sp;
02317   if (argc + (struct_addr ? 1 : 0) > 4)
02318     sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE;
02319 
02320   arg_reg = MEP_R1_REGNUM;
02321   arg_stack = sp;
02322 
02323   /* If we're returning a structure by value, push the pointer to the
02324      buffer as the first argument.  */
02325   if (struct_return)
02326     {
02327       regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr);
02328       arg_reg++;
02329     }
02330 
02331   for (i = 0; i < argc; i++)
02332     {
02333       ULONGEST value;
02334 
02335       /* Arguments that fit in a GPR get expanded to fill the GPR.  */
02336       if (TYPE_LENGTH (value_type (argv[i])) <= MEP_GPR_SIZE)
02337         value = extract_unsigned_integer (value_contents (argv[i]),
02338                                           TYPE_LENGTH (value_type (argv[i])),
02339                                           byte_order);
02340 
02341       /* Arguments too large to fit in a GPR get copied to the stack,
02342          and we pass a pointer to the copy.  */
02343       else
02344         value = copy[i];
02345 
02346       /* We use $1 -- $4 for passing arguments, then use the stack.  */
02347       if (arg_reg <= MEP_R4_REGNUM)
02348         {
02349           regcache_cooked_write_unsigned (regcache, arg_reg, value);
02350           arg_reg++;
02351         }
02352       else
02353         {
02354           gdb_byte buf[MEP_GPR_SIZE];
02355           store_unsigned_integer (buf, MEP_GPR_SIZE, byte_order, value);
02356           write_memory (arg_stack, buf, MEP_GPR_SIZE);
02357           arg_stack += MEP_GPR_SIZE;
02358         }
02359     }
02360 
02361   gdb_assert (arg_stack <= arg_stack_end);
02362 
02363   /* Set the return address.  */
02364   regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr);
02365 
02366   /* Update the stack pointer.  */
02367   regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp);
02368   
02369   return sp;
02370 }
02371 
02372 
02373 static struct frame_id
02374 mep_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
02375 {
02376   CORE_ADDR sp = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM);
02377   return frame_id_build (sp, get_frame_pc (this_frame));
02378 }
02379 
02380 
02381 
02382 /* Initialization.  */
02383 
02384 
02385 static struct gdbarch *
02386 mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
02387 {
02388   struct gdbarch *gdbarch;
02389   struct gdbarch_tdep *tdep;
02390 
02391   /* Which me_module are we building a gdbarch object for?  */
02392   CONFIG_ATTR me_module;
02393 
02394   /* If we have a BFD in hand, figure out which me_module it was built
02395      for.  Otherwise, use the no-particular-me_module code.  */
02396   if (info.abfd)
02397     {
02398       /* The way to get the me_module code depends on the object file
02399          format.  At the moment, we only know how to handle ELF.  */
02400       if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
02401         me_module = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK;
02402       else
02403         me_module = CONFIG_NONE;
02404     }
02405   else
02406     me_module = CONFIG_NONE;
02407 
02408   /* If we're setting the architecture from a file, check the
02409      endianness of the file against that of the me_module.  */
02410   if (info.abfd)
02411     {
02412       /* The negations on either side make the comparison treat all
02413          non-zero (true) values as equal.  */
02414       if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module))
02415         {
02416           const char *module_name = me_module_name (me_module);
02417           const char *module_endianness
02418             = me_module_big_endian (me_module) ? "big" : "little";
02419           const char *file_name = bfd_get_filename (info.abfd);
02420           const char *file_endianness
02421             = bfd_big_endian (info.abfd) ? "big" : "little";
02422           
02423           fputc_unfiltered ('\n', gdb_stderr);
02424           if (module_name)
02425             warning (_("the MeP module '%s' is %s-endian, but the executable\n"
02426                        "%s is %s-endian."),
02427                      module_name, module_endianness,
02428                      file_name, file_endianness);
02429           else
02430             warning (_("the selected MeP module is %s-endian, but the "
02431                        "executable\n"
02432                        "%s is %s-endian."),
02433                      module_endianness, file_name, file_endianness);
02434         }
02435     }
02436 
02437   /* Find a candidate among the list of architectures we've created
02438      already.  info->bfd_arch_info needs to match, but we also want
02439      the right me_module: the ELF header's e_flags field needs to
02440      match as well.  */
02441   for (arches = gdbarch_list_lookup_by_info (arches, &info); 
02442        arches != NULL;
02443        arches = gdbarch_list_lookup_by_info (arches->next, &info))
02444     if (gdbarch_tdep (arches->gdbarch)->me_module == me_module)
02445       return arches->gdbarch;
02446 
02447   tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
02448   gdbarch = gdbarch_alloc (&info, tdep);
02449 
02450   /* Get a CGEN CPU descriptor for this architecture.  */
02451   {
02452     const char *mach_name = info.bfd_arch_info->printable_name;
02453     enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG
02454                                ? CGEN_ENDIAN_BIG
02455                                : CGEN_ENDIAN_LITTLE);
02456 
02457     tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
02458                                         CGEN_CPU_OPEN_ENDIAN, endian,
02459                                         CGEN_CPU_OPEN_END);
02460   }
02461 
02462   tdep->me_module = me_module;
02463 
02464   /* Register set.  */
02465   set_gdbarch_read_pc (gdbarch, mep_read_pc);
02466   set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS);
02467   set_gdbarch_pc_regnum (gdbarch, MEP_PC_REGNUM);
02468   set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM);
02469   set_gdbarch_register_name (gdbarch, mep_register_name);
02470   set_gdbarch_register_type (gdbarch, mep_register_type);
02471   set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS);
02472   set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read);
02473   set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write);
02474   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum);
02475   set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum);
02476 
02477   set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p);
02478   reggroup_add (gdbarch, all_reggroup);
02479   reggroup_add (gdbarch, general_reggroup);
02480   reggroup_add (gdbarch, save_reggroup);
02481   reggroup_add (gdbarch, restore_reggroup);
02482   reggroup_add (gdbarch, mep_csr_reggroup);
02483   reggroup_add (gdbarch, mep_cr_reggroup);
02484   reggroup_add (gdbarch, mep_ccr_reggroup);
02485 
02486   /* Disassembly.  */
02487   set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn); 
02488 
02489   /* Breakpoints.  */
02490   set_gdbarch_breakpoint_from_pc (gdbarch, mep_breakpoint_from_pc);
02491   set_gdbarch_decr_pc_after_break (gdbarch, 0);
02492   set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue);
02493 
02494   /* Frames and frame unwinding.  */
02495   frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind);
02496   set_gdbarch_unwind_pc (gdbarch, mep_unwind_pc);
02497   set_gdbarch_unwind_sp (gdbarch, mep_unwind_sp);
02498   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
02499   set_gdbarch_frame_args_skip (gdbarch, 0);
02500 
02501   /* Return values.  */
02502   set_gdbarch_return_value (gdbarch, mep_return_value);
02503   
02504   /* Inferior function calls.  */
02505   set_gdbarch_frame_align (gdbarch, mep_frame_align);
02506   set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call);
02507   set_gdbarch_dummy_id (gdbarch, mep_dummy_id);
02508 
02509   return gdbarch;
02510 }
02511 
02512 /* Provide a prototype to silence -Wmissing-prototypes.  */
02513 extern initialize_file_ftype _initialize_mep_tdep;
02514 
02515 void
02516 _initialize_mep_tdep (void)
02517 {
02518   mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
02519   mep_cr_reggroup  = reggroup_new ("cr", USER_REGGROUP); 
02520   mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP);
02521 
02522   register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init);
02523 
02524   mep_init_pseudoregister_maps ();
02525 }
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