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GDB (API)
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GDB (API)
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00001 /* 00002 * Helper cpuid.h file copied from gcc-4.8.0. Code in gdb should not 00003 * include this directly, but pull in i386-cpuid.h and use that func. 00004 */ 00005 /* 00006 * Copyright (C) 2007-2013 Free Software Foundation, Inc. 00007 * 00008 * This file is free software; you can redistribute it and/or modify it 00009 * under the terms of the GNU General Public License as published by the 00010 * Free Software Foundation; either version 3, or (at your option) any 00011 * later version. 00012 * 00013 * This file is distributed in the hope that it will be useful, but 00014 * WITHOUT ANY WARRANTY; without even the implied warranty of 00015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00016 * General Public License for more details. 00017 * 00018 * Under Section 7 of GPL version 3, you are granted additional 00019 * permissions described in the GCC Runtime Library Exception, version 00020 * 3.1, as published by the Free Software Foundation. 00021 * 00022 * You should have received a copy of the GNU General Public License and 00023 * a copy of the GCC Runtime Library Exception along with this program; 00024 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 00025 * <http://www.gnu.org/licenses/>. 00026 */ 00027 00028 /* %ecx */ 00029 #define bit_SSE3 (1 << 0) 00030 #define bit_PCLMUL (1 << 1) 00031 #define bit_LZCNT (1 << 5) 00032 #define bit_SSSE3 (1 << 9) 00033 #define bit_FMA (1 << 12) 00034 #define bit_CMPXCHG16B (1 << 13) 00035 #define bit_SSE4_1 (1 << 19) 00036 #define bit_SSE4_2 (1 << 20) 00037 #define bit_MOVBE (1 << 22) 00038 #define bit_POPCNT (1 << 23) 00039 #define bit_AES (1 << 25) 00040 #define bit_XSAVE (1 << 26) 00041 #define bit_OSXSAVE (1 << 27) 00042 #define bit_AVX (1 << 28) 00043 #define bit_F16C (1 << 29) 00044 #define bit_RDRND (1 << 30) 00045 00046 /* %edx */ 00047 #define bit_CMPXCHG8B (1 << 8) 00048 #define bit_CMOV (1 << 15) 00049 #define bit_MMX (1 << 23) 00050 #define bit_FXSAVE (1 << 24) 00051 #define bit_SSE (1 << 25) 00052 #define bit_SSE2 (1 << 26) 00053 00054 /* Extended Features */ 00055 /* %ecx */ 00056 #define bit_LAHF_LM (1 << 0) 00057 #define bit_ABM (1 << 5) 00058 #define bit_SSE4a (1 << 6) 00059 #define bit_PRFCHW (1 << 8) 00060 #define bit_XOP (1 << 11) 00061 #define bit_LWP (1 << 15) 00062 #define bit_FMA4 (1 << 16) 00063 #define bit_TBM (1 << 21) 00064 00065 /* %edx */ 00066 #define bit_MMXEXT (1 << 22) 00067 #define bit_LM (1 << 29) 00068 #define bit_3DNOWP (1 << 30) 00069 #define bit_3DNOW (1 << 31) 00070 00071 /* Extended Features (%eax == 7) */ 00072 #define bit_FSGSBASE (1 << 0) 00073 #define bit_BMI (1 << 3) 00074 #define bit_HLE (1 << 4) 00075 #define bit_AVX2 (1 << 5) 00076 #define bit_BMI2 (1 << 8) 00077 #define bit_RTM (1 << 11) 00078 #define bit_RDSEED (1 << 18) 00079 #define bit_ADX (1 << 19) 00080 00081 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ 00082 #define bit_XSAVEOPT (1 << 0) 00083 00084 /* Signatures for different CPU implementations as returned in uses 00085 of cpuid with level 0. */ 00086 #define signature_AMD_ebx 0x68747541 00087 #define signature_AMD_ecx 0x444d4163 00088 #define signature_AMD_edx 0x69746e65 00089 00090 #define signature_CENTAUR_ebx 0x746e6543 00091 #define signature_CENTAUR_ecx 0x736c7561 00092 #define signature_CENTAUR_edx 0x48727561 00093 00094 #define signature_CYRIX_ebx 0x69727943 00095 #define signature_CYRIX_ecx 0x64616574 00096 #define signature_CYRIX_edx 0x736e4978 00097 00098 #define signature_INTEL_ebx 0x756e6547 00099 #define signature_INTEL_ecx 0x6c65746e 00100 #define signature_INTEL_edx 0x49656e69 00101 00102 #define signature_TM1_ebx 0x6e617254 00103 #define signature_TM1_ecx 0x55504361 00104 #define signature_TM1_edx 0x74656d73 00105 00106 #define signature_TM2_ebx 0x756e6547 00107 #define signature_TM2_ecx 0x3638784d 00108 #define signature_TM2_edx 0x54656e69 00109 00110 #define signature_NSC_ebx 0x646f6547 00111 #define signature_NSC_ecx 0x43534e20 00112 #define signature_NSC_edx 0x79622065 00113 00114 #define signature_NEXGEN_ebx 0x4778654e 00115 #define signature_NEXGEN_ecx 0x6e657669 00116 #define signature_NEXGEN_edx 0x72446e65 00117 00118 #define signature_RISE_ebx 0x65736952 00119 #define signature_RISE_ecx 0x65736952 00120 #define signature_RISE_edx 0x65736952 00121 00122 #define signature_SIS_ebx 0x20536953 00123 #define signature_SIS_ecx 0x20536953 00124 #define signature_SIS_edx 0x20536953 00125 00126 #define signature_UMC_ebx 0x20434d55 00127 #define signature_UMC_ecx 0x20434d55 00128 #define signature_UMC_edx 0x20434d55 00129 00130 #define signature_VIA_ebx 0x20414956 00131 #define signature_VIA_ecx 0x20414956 00132 #define signature_VIA_edx 0x20414956 00133 00134 #define signature_VORTEX_ebx 0x74726f56 00135 #define signature_VORTEX_ecx 0x436f5320 00136 #define signature_VORTEX_edx 0x36387865 00137 00138 #if defined(__i386__) && defined(__PIC__) 00139 /* %ebx may be the PIC register. */ 00140 #if __GNUC__ >= 3 00141 #define __cpuid(level, a, b, c, d) \ 00142 __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ 00143 "cpuid\n\t" \ 00144 "xchg{l}\t{%%}ebx, %k1\n\t" \ 00145 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00146 : "0" (level)) 00147 00148 #define __cpuid_count(level, count, a, b, c, d) \ 00149 __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t" \ 00150 "cpuid\n\t" \ 00151 "xchg{l}\t{%%}ebx, %k1\n\t" \ 00152 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00153 : "0" (level), "2" (count)) 00154 #else 00155 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 00156 nor alternatives in i386 code. */ 00157 #define __cpuid(level, a, b, c, d) \ 00158 __asm__ ("xchgl\t%%ebx, %k1\n\t" \ 00159 "cpuid\n\t" \ 00160 "xchgl\t%%ebx, %k1\n\t" \ 00161 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00162 : "0" (level)) 00163 00164 #define __cpuid_count(level, count, a, b, c, d) \ 00165 __asm__ ("xchgl\t%%ebx, %k1\n\t" \ 00166 "cpuid\n\t" \ 00167 "xchgl\t%%ebx, %k1\n\t" \ 00168 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00169 : "0" (level), "2" (count)) 00170 #endif 00171 #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__) 00172 /* %rbx may be the PIC register. */ 00173 #define __cpuid(level, a, b, c, d) \ 00174 __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ 00175 "cpuid\n\t" \ 00176 "xchg{q}\t{%%}rbx, %q1\n\t" \ 00177 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00178 : "0" (level)) 00179 00180 #define __cpuid_count(level, count, a, b, c, d) \ 00181 __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t" \ 00182 "cpuid\n\t" \ 00183 "xchg{q}\t{%%}rbx, %q1\n\t" \ 00184 : "=a" (a), "=&r" (b), "=c" (c), "=d" (d) \ 00185 : "0" (level), "2" (count)) 00186 #else 00187 #define __cpuid(level, a, b, c, d) \ 00188 __asm__ ("cpuid\n\t" \ 00189 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 00190 : "0" (level)) 00191 00192 #define __cpuid_count(level, count, a, b, c, d) \ 00193 __asm__ ("cpuid\n\t" \ 00194 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 00195 : "0" (level), "2" (count)) 00196 #endif 00197 00198 /* Return highest supported input value for cpuid instruction. ext can 00199 be either 0x0 or 0x8000000 to return highest supported value for 00200 basic or extended cpuid information. Function returns 0 if cpuid 00201 is not supported or whatever cpuid returns in eax register. If sig 00202 pointer is non-null, then first four bytes of the signature 00203 (as found in ebx register) are returned in location pointed by sig. */ 00204 00205 static __inline unsigned int 00206 __get_cpuid_max (unsigned int __ext, unsigned int *__sig) 00207 { 00208 unsigned int __eax, __ebx, __ecx, __edx; 00209 00210 #ifdef __i386__ 00211 /* See if we can use cpuid. On AMD64 we always can. */ 00212 #if __GNUC__ >= 3 00213 __asm__ ("pushf{l|d}\n\t" 00214 "pushf{l|d}\n\t" 00215 "pop{l}\t%0\n\t" 00216 "mov{l}\t{%0, %1|%1, %0}\n\t" 00217 "xor{l}\t{%2, %0|%0, %2}\n\t" 00218 "push{l}\t%0\n\t" 00219 "popf{l|d}\n\t" 00220 "pushf{l|d}\n\t" 00221 "pop{l}\t%0\n\t" 00222 "popf{l|d}\n\t" 00223 : "=&r" (__eax), "=&r" (__ebx) 00224 : "i" (0x00200000)); 00225 #else 00226 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax 00227 nor alternatives in i386 code. */ 00228 __asm__ ("pushfl\n\t" 00229 "pushfl\n\t" 00230 "popl\t%0\n\t" 00231 "movl\t%0, %1\n\t" 00232 "xorl\t%2, %0\n\t" 00233 "pushl\t%0\n\t" 00234 "popfl\n\t" 00235 "pushfl\n\t" 00236 "popl\t%0\n\t" 00237 "popfl\n\t" 00238 : "=&r" (__eax), "=&r" (__ebx) 00239 : "i" (0x00200000)); 00240 #endif 00241 00242 if (!((__eax ^ __ebx) & 0x00200000)) 00243 return 0; 00244 #endif 00245 00246 /* Host supports cpuid. Return highest supported cpuid input value. */ 00247 __cpuid (__ext, __eax, __ebx, __ecx, __edx); 00248 00249 if (__sig) 00250 *__sig = __ebx; 00251 00252 return __eax; 00253 } 00254 00255 /* Return cpuid data for requested cpuid level, as found in returned 00256 eax, ebx, ecx and edx registers. The function checks if cpuid is 00257 supported and returns 1 for valid cpuid information or 0 for 00258 unsupported cpuid level. All pointers are required to be non-null. */ 00259 00260 static __inline int 00261 __get_cpuid (unsigned int __level, 00262 unsigned int *__eax, unsigned int *__ebx, 00263 unsigned int *__ecx, unsigned int *__edx) 00264 { 00265 unsigned int __ext = __level & 0x80000000; 00266 00267 if (__get_cpuid_max (__ext, 0) < __level) 00268 return 0; 00269 00270 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); 00271 return 1; 00272 }
1.7.6.1
